SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 729

• Manufacturer Part Number: SAM9261
• Manufacturer: Atmel Corporation

Specifications of SAM9261

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 160
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6062N–ATARM–3-Oct-11
Doc. Rev.
6062G
22-Feb-07
Comments
Updated
Management Controller Block Diagram,” on page
EBI: In
on CE connection and NAND Flash.
BootROM: Updated DataFlash support in
RSTC: In
counter for crystal oscillator.
SMC: Added information on boot
SDRAMC: Change to
addition of note
PMC: Updated
Figure 24-3, “Typical Crystal Connection,” on page
Updated
Updated information on HClocks in
Updated information on enable/disable in
PIO:
Section 29.4.5 “Synchronous Data Output” on page
Section 29.6 “Parallel Input/Output Controller (PIO) User Interface” on page
updated on PIO_PSR, PIO_ODSR, PIO_PDSR in Register Mapping table.
TC: Added information on compare register B and waveform generation in
“External Event/Trigger Conditions” on page
“EEVT: External Event Selection” on page 530
on page 529
Added
UHP: Corrected signal name in block diagram
Updated schematic
page 574
page
UDP: All sections and information on wake-up/remote wake-up updated.
Section 37.6.10 “UDP Endpoint Control and Status Register” on page
Read values in FORCESTALL bit .
Section 37.6.2 “UDP Global State Register” on page 596
updated.
Note added to TXVDIS bit description in
page 612
In
1.2V. In
static current value for V
Table 38-2, “DC Characteristics,” on page
Figure 29-3, “I/O Line Control Logic,” on page 328
574.
Figure 34-2, “Clock Chaining Selection,” on page 511
Table 20-4, “EBI Pins and External Devices Connections,” on page
Table 39-3, “Power Consumption for Different Modes,” on page
Section 9.6 ”Power Management Controller” on page 25
Section 24.3.1 “Main Oscillator Connections” on page
Section 14.3.1 “Reset Controller Overview” on page 94
and added text on termination serial resistor in
describing USB pullup effect on USB reset.
to further clarify.
Figure 24-1, “Typical Slow Clock Crystal Oscillator Connection,” on page 235
(1)
on
Figure 36-4, “Board Schematic to Interface UHP Device Controller,” on
page
Step 5
VDDCORE
204.
in
Section 22.4.1 “SDRAM Device Initialization” on page
= 1.2V.
inSection 21.7.2.1 “Byte Write Access” on page
Section 25.1 “Overview” on page
Section 37.6.12 “UDP Transceiver Control Register” on
Section 25.3 “Processor Clock Controller” on page
Table 13-2, “DataFlash Device,” on page
522. Added Note
633, updated static current value for V
Figure 36-1 on page 571
in
“TC Channel Mode Register: Waveform Mode”
25.
236.
330, PIO_OWSR typo corrected.
change to I/O Line Control Logic.
Section 36.5 “Typical Connection” on
activity of ESR and RMWUPE bits
to demonstrate clock chaining.
(1)
236.
to Register Bit Description
added information on startup
and
240.
606, changes to Write and
Figure 9-3, “Power
to UHPCK.
669, updated Quasi
Section 34.5.12
139, added Note
334, footnotes
AT91SAM9261
163.
VDDCORE
84.
203;
=
241.
and
(3)
Change
Request
Ref
3491
3894
4183
3005
3252
3305
3861
3832
3491
3835
3053
3289
3974
2704
3342
2924
3365
3048
3055
3806
729