SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 1234
SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
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- SAM9261 PDF datasheet #3
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Table 46-23. In Full Speed
46.13 Analog-to-Digital Converter (ADC)
Table 46-24. Channel Conversion Time and ADC Clock
Note:
1234
1234
Symbol
t
t
t
Parameter
ADC Clock Frequency
Startup Time
Track and Hold Acquisition Time (TTH)
Conversion Time (TCT)
Throughput Rate
FR
FE
FRFM
1. The Track-and-Hold Acquisition Time is given by:
SAM9G35
SAM9G35
The ADC internal clock is divided by 2 in order to generate a clock with a duty cycle of 75%. So the maximum conversion
time is given by:
The full speed is obtained for an input source impedance of < 50
In order to make the TSADC work properly, the SHTIM field in TSADCC Mode Register is to be calculated according to this
Track and Hold Acquisition Time, also called Sampled and Hold Time.
TTH (ns)
Parameter
Transition Rise Time
Transition Fall Time
Rise/Fall time Matching
TCT μs
=
=
Table 46-25. External Voltage Reference Input
Parameter
ADVREF Input Voltage Range
ADVREF Average Current
Current Consumption on VDDANA
500
---------- - MHz
Fclk
23
+
0.12
Z
Conditions
10-bit resolution mode
Return from Idle Mode
ADC Clock = 13.2 MHz
ADC Clock = 13.2 MHz
ADC Clock = 5 MHz
ADC Clock = 13.2 MHz
ADC Clock = 5 MHz
IN
Conditions
C
C
LOAD
LOAD
= 50 pF
= 50 pF
(1)
(1)
Conditions
(1)
(1)
(1)
maximum, or TTH = 500 ns.
Min
2.4
Min
0.5
Min
90
4
4
Typ
Typ
Typ
VDDANA
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Max
600
600
111.11
Max
13.2
1.74
440
192
Max
4.6
40
20
20
Units
Units
kSPS
MHz
Unit
μA
μA
V
μs
μs
μs
ns
ns
%
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