SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 741
SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
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- SAM9261 PDF datasheet #3
- SAM9G20 PDF datasheet #4
- SAM9G20 PDF datasheet #5
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37.6.3
37.6.3.1
37.6.3.2
37.6.3.3
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
PWM Controller Operations
Initialization
Changing the Duty Cycle or the Period
Source Clock Selection Criteria
Before enabling the output channel, this channel must have been configured by the software
application:
It is possible to synchronize different channels by enabling them at the same time by means of
writing simultaneously several CHIDx bits in the PWM_ENA register.
The large number of source clocks can make selection difficult. The relationship between the
value in the Period Register (PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can
help the user in choosing. The event number written in the Period Register gives the PWM accu-
racy. The Duty Cycle quantum cannot be lower than 1/PWM_CPRDx value. The higher the value
of PWM_CPRDx, the greater the PWM accuracy.
For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value
between 1 up to 14 in PWM_CDTYx Register. The resulting duty cycle quantum cannot be lower
than 1/15 of the PWM period.
It is possible to modulate the output waveform duty cycle or period.
To prevent unexpected output waveform, the user must use the update register (PWM_CUPDx)
to change waveform parameters while the channel is still enabled. The user can write a new
period value or duty cycle value in the update register (PWM_CUPDx). This register holds the
new value until the end of the current cycle and updates the value for the next cycle. Depending
on the CPD field in the PWM_CMRx register, PWM_CUPDx either updates PWM_CPRDx or
PWM_CDTYx. Note that even if the update register is used, the period must not be smaller than
the duty cycle.
• Configuration of the clock generator if DIVA and DIVB are required
• Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
• Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx
• Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in
• Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register).
• Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx
• Enable Interrupts (Writing CHIDx in the PWM_IER register)
• Enable the PWM channel (Writing CHIDx in the PWM_ENA register)
• In such a situation, all channels may have the same clock selector configuration and the
register)
PWM_CPRDx Register is possible while the channel is disabled. After validation of the
channel, the user must use PWM_CUPDx Register to update PWM_CPRDx as explained
below.
Writing in PWM_CDTYx Register is possible while the channel is disabled. After validation of
the channel, the user must use PWM_CUPDx Register to update PWM_CDTYx as explained
below.
register)
same period specified.
SAM9G35
SAM9G35
741
741
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