SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 459
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SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G20 PDF datasheet #4
- SAM9G20 PDF datasheet #5
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• CAS: CAS Latency
The reset value is 2 cycles.
• DLL: Reset DLL
Reset value is 0.
This field defines the value of Reset DLL.
0 = Disable DLL reset.
1 = Enable DLL reset.
This value is used during the power-up sequence.
Note: This field is found only in DDR2-SDRAM devices.
• DIC/DS: Output Driver Impedance Control
Reset value is 0.
This field defines the output drive strength.
0 = Normal driver strength.
1 = Weak driver strength.
This value is used during the power-up sequence. This parameter is found in the datasheet as DIC or DS.
Note: This field is found only in DDR2-SDRAM devices.
• DIS_DLL: Disable DLL
Reset value is 0.
0 = Enable DLL
1 = Disable DLL
Note: This field is found only in DDR2-SDRAM devices.
• OCD: Off-chip Driver
Reset value is 7.
Note: OCD is NOT supported by the controller, but these values MUST be programmed during the initialization sequence.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
CAS
000
001
010
011
100
101
110
111
DDR2 CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3
SDR CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
SAM9G35
SAM9G35
459
459
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