SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 453

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SAM9G25

Manufacturer Part Number
SAM9G25
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G25

Flash (kbytes)
0 Kbytes
Pin Count
247
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Figure 30-22. Power-down Entry/Exit, Timeout = 0
30.5.4.3
Figure 30-23. Deep Power-down Mode Entry
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
COMMAND
DQS[1:0]
DM[1:0]
SDCLK
BA[1:0]
D[15:0]
A[12:0]
COMMAND
CKE
Deep Power-down Mode
DQS[1:0]
DM[1:0]
SDCLK
BA[1:0]
A[12:0]
D[15:0]
CKE
NOP READ
0
3
0
3
READ
The deep power-down mode is a new feature of the Low-power SDRAM. When this mode is
activated, all internal voltage generators inside the device are stopped and all data is lost.
This mode is activated by setting the low-power command bits [LPCB] to ‘11’. When this mode is
enabled, the DDRSDRC leaves normal mode (mode == 000) and the controller is frozen. To exit
deep power-down mode, the low-power bits (LPCB) must be set to “00”, an initialization
sequence must be generated by software. See
tialization” on page
BST
BST
NOP
NOP
Da
435.
Da
Db
Db
Entry power down mode
Section 30.4.2 “Low-power DDR1-SDRAM Ini-
PRCHG
NOP
Exit power down mode
Trp
DEEPOWER
READ
Enter Deep
Power-down
Mode
SAM9G25
SAM9G25
NOP
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