SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 922

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SAM9G25

Manufacturer Part Number
SAM9G25
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G25

Flash (kbytes)
0 Kbytes
Pin Count
247
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
41.6
41.6.1
Figure 41-2. Sequence of ADC conversions
41.6.2
41.6.3
922
922
(Hard or Soft)
Trigger event
Functional Description
ADC_Start
ADCClock
ADC_SEL
ADC_ON
ADC_eoc
SAM9G25
SAM9G25
Analog-to-digital Conversion
Conversion Reference
Conversion Resolution
DRDY
LCDR
The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-
bit digital data requires Tracking Clock cycles as defined in the field TRACKTIM of the
Mode Register” on page 930
same register. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register
(ADC_MR). The tracking phase starts during the conversion of the previous channel. If the track-
ing time is longer than the conversion time, the tracking phase is extended to the end of the
previous conversion.
The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/512, if PRESCAL is set to
255 (0xFF). PRESCAL must be programmed in order to provide an ADC clock frequency
according to the parameters given in the product Electrical Characteristics section.
The conversion is performed on a full range between 0V and the reference voltage pin ADVREF.
Analog inputs between these voltages convert to values based on a linear conversion.
The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the
LOWRES bit in the ADC Mode Register (ADC_MR). By default, after a reset, the resolution is
the highest and the DATA field in the data registers is fully used. By setting the LOWRES bit, the
ADC switches to the lowest resolution and the conversion results can be read in the lowest sig-
nificant bits of the data registers. The two highest bits of the DATA field in the corresponding
ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0.
(and tracking of CH0)
CH0
Start Up Time
Conversion of CH0
and Transfer Clock cycles as defined in the field TRANSFER of the
CH0
CH1
Tracking of CH1
Conversion of CH1
CH2
CH1
Tracking of CH2
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
“ADC

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