SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 997

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

44.3
Figure 44-2. Image Sensor Interface Block Diagram
44.4
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
Hsync/Len
Vsync/Fen
RGB
YCbCr 4:2:2
CMOS
sensor
Pixel input
up to 12 bit
CMOS
sensor
pixel clock
input
8:8:8
5:6:5
Block Diagram
Functional Description
Decoder(SAV/EAV)
Embedded Timing
Timing Signals
Pixel Sampling
Frame Rate
CCIR-656
Interface
Module
The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit
mode compliant sensors and up to 12-bit grayscale sensors. It receives the image data stream
from the image sensor on the 12-bit data bus.
This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the
pixel clock. The reduced pin count alternative for synchronization is supported for sensors that
embed SAV (start of active video) and EAV (end of active video) delimiters in the data stream.
The Image Sensor Interface interrupt line is connected to the Advanced Interrupt Controller and
can trigger an interrupt at the beginning of each frame and at the end of a DMA frame transfer. If
the SAV/EAV synchronization is used, an interrupt can be triggered on each delimiter event.
For 8-bit color sensors, the data stream received can be in several possible formats: YCbCr
4:2:2, RGB 8:8:8, RGB 5:6:5 and may be processed before the storage in memory. When the
preview DMA channel is configured and enabled, the preview path is activated and an ‘RGB
frame’ is moved to memory. The preview path frame rate is configured with the FRATE field of
the ISI_CFG1 register. When the codec DMA channel is configured and enabled, the codec path
is activated and a ‘YCbCr 4:2:2 frame’ is captured as soon as the ISI_CDC field of the ISI_CTRL
register is set to 1.
When the FULL field of the ISI_CFG1 register is set to 1, both preview DMA channel and codec
DMA channel can operate simultaneously. When the FULL field of the ISI_CFG1 register is set
to 0, a hardware scheduler checks the FRATE field. If its value is zero, a preview frame is
skipped and a codec frame is moved to memory instead. If its value is different from zero, at
least one free frame slot is available. The scheduler postpones the codec frame to that free
available frame slot.
codec_on
Clipping + Color
Clipping + Color
YCC to RGB
Preview path
Conversion
Codec path
RGB to YCC
Conversion
Controller
Interrupt
Camera
2-D Image
From
Rx buffers
Scaler
Camera
Interrupt Request Line
Formatter
Formatter
Packed
Pixel
Clock Domain
Pixel
Rx Direct
Rx Direct
Capture
Display
FIFO
FIFO
APB
Clock Domain
AHB
Clock Domain
Registers
Config
Arbiter
Video
Core
SAM9G25
SAM9G25
Interface
Interface
Camera
Support
Master
Scatter
Mode
AHB
APB
997
997