SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 18

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6. I/O Line Considerations
6.1
6.2
6.3
6.4
6.5
7. Processor and Architecture
7.1
18
JTAG Port Pins
Test Pin
Reset Pins
PIO Controllers
Shutdown Logic Pins
ARM926EJ-S Processor
AT91SAM9R64/RL64
TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors.
TDO is an output, driven at up to VDDIOP, and have no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left uncon-
nected for normal operations.
All the JTAG signals are supplied with VDDIOP except JTAGSEL supplied by VDDBU.
The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma-
nent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal
operations. Driving this line at a high level leads to unpredictable results.
This pin is supplied with VDDBU.
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven
with voltage at up to VDDIOP.
As the product integrates power-on reset cells, which manages the processor and the JTAG
reset, the NRST and NTRST pin can be left unconnected.
The NRST and NTRST pins integrates a permanent pull-up resistor of 100 kΩ typical to
VDDIOP.
The NRST signal is inserted in the Boundary Scan.
All the I/O lines which are managed by the PIO Controllers integrate a programmable pull-up
resistor. Refer to the section “AT91SAM9R64/RL64 Electrical Characteristics” in the product
datasheet for more details.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral
at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing
tables.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
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RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
acceleration
Two Instruction Sets
6289CS–ATARM–28-May-09