SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 24

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 8-2.
Table 8-3.
Note:
24
Decoded
SRAM A
SRAM B
SRAM C
(DTCM)
Internal
Internal
Internal
(ITCM)
(AHB)
Area
1. Configuration after reset.
Internal SRAM B (DTCM) size
AT91SAM9R64/RL64
0x0030 C000
0x0010 0000
0x0010 4000
0x0020 0000
0x0020 4000
0x0030 0000
0x0030 4000
0x0030 8000
Internal SRAM Block Size
Address
16-Kbyte Block Allocation example
Remaining Internal SRAM C
Within the 64Kbyte SRAM size available, the amount of memory assigned to each block is soft-
ware programmable as a multiple of 16K Bytes according to
size of the Internal SRAM C according to the size of the Internal SRAM A and the Internal SRAM
B.
At reset, the whole memory is assigned to Internal SRAM C.
The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and
when the user dynamically changes the Internal SRAM configuration, the new 16-Kbyte block
organization may affect the previous configuration from a software point of view.
Table 8-3
assignments.
• Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block
• Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap
A = 64K
D = 0K
anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is
also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus
at address 0x0020 0000.
Command is performed, this SRAM block is accessible through the AHB bus at address
0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes
accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926
Data Masters.
I = 0K
RB0
RB3
RB2
RB1
(1)
illustrates different configurations and the related 16-Kbyte blocks (RB0 to RB3)
A = 48K
I = 16K
D = 0K
RB1
RB3
RB2
RB0
Configuration examples and related 16-Kbyte block assignments
A = 32K
16K Bytes
32K Bytes
D = 0K
I =32K
RB1
RB0
RB3
RB2
0
D = 16K
A = 48K
I = 0K
RB3
RB2
RB1
RB0
64K Bytes
48K Bytes
32K Bytes
D = 16K
A = 32K
I = 16K
RB1
RB3
RB2
RB0
0
Internal SRAM A (ITCM) Size
D = 16K
A = 16K
I = 32K
RB1
RB0
RB2
RB3
Table
16K Bytes
48K Bytes
32K Bytes
16K Bytes
D = 32K
A = 32K
8-2. This Table provides the
I = 0K
RB3
RB2
RB1
RB0
6289CS–ATARM–28-May-09
D = 32K
A = 16K
I = 16K
RB1
RB3
RB2
RB0
32K Bytes
16K Bytes
32K Bytes
0K Bytes
D = 32K
I = 32K
A = 0K
RB1
RB0
RB3
RB2