SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 1057
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 1057 of 1325
- Download datasheet (30Mb)
45. Ethernet MAC 10/100 (EMAC)
45.1
45.2
11055B–ATARM–22-Sep-11
11055B–ATARM–22-Sep-11
Description
Embedded Characteristics
The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 stan-
dard using an address checker, statistics and control registers, receive and transmit blocks, and
a DMA interface.
The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash regis-
ter for matching multicast and unicast addresses. It can recognize the broadcast address of all
ones, copy all frames, and act on an external address match signal.
The statistics register block contains registers for counting various types of event associated
with transmit and receive operations. These registers, along with the status words stored in the
receive buffer list, enable software to generate network management statistics compatible with
IEEE 802.3.
• Supports MII Interface to the physical layer
• Compatible with IEEE Standard 802.3
• 10 and 100 Mbit/s Operation
• Full- and Half-duplex Operation
• Statistics Counter Registers
• Interrupt Generation to Signal Receive and Transmit Completion
• DMA Master on Receive and Transmit Channels
• Transmit and Receive FIFOs
• Automatic Pad and CRC Generation on Transmitted Frames
• Automatic Discard of Frames Received with Errors
• Address Checking Logic Supports Up to Four Specific 48-bit Addresses
• Supports Promiscuous Mode Where All Valid Received Frames are Copied to Memory
• Hash Matching of Unicast and Multicast Destination Addresses
• Physical Layer Management through MDIO Interface
• Half-duplex Flow Control by Forcing Collisions on Incoming Frames
•
•
• Multiple Buffers per Receive and Transmit Frame
• Jumbo Frames Up to 10240 bytes Supported
Full-duplex Flow Control with Recognition of Incoming Pause Frames
Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and
Frames
SAM9X35
SAM9X35
Priority Tagged
1057
1057
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