SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 527
SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 527 of 1325
- Download datasheet (30Mb)
32.3
Figure 32-3. Block Diagram
11055B–ATARM–22-Sep-11
11055B–ATARM–22-Sep-11
AHB
AHB
AHB
AHB
Block Diagram
Master
Master
Slave
Slave
Master Block
Master Block
Slave Block
Slave Block
Registers
Registers
OHCI
EHCI
HCI
HCI
HCI
HCI
Control
Control
Access to the USB host operational registers is achieved through the AHB bus slave interface.
The Open HCI host controller and Enhanced HCI host controller initialize master DMA transfers
through the AHB bus master interface as follows:
Memory access errors (abort, misalignment) lead to an “Unrecoverable Error” indicated by the
corresponding flag in the host controller operational registers.
The USB root hub is integrated in the USB host. Several USB downstream ports are available.
The number of downstream ports can be determined by the software driver reading the root
hub’s operational registers. Device connection is automatically detected by the USB host port
logic.
Data
Data
• Fetches endpoint descriptors and transfer descriptors
• Access to endpoint data from system memory
• Access to the HC communication area
• Write status and retire transfer descriptor
List Processor
FIFO 64 x 8
Regsisters
Generator
Processor
ED & TD
Block
SOF
List
Root Hub
Host SIE
Packet
Buffer
FIFO
and
Hub Registers
PORT S/M 0
PORT S/M 1
PORT S/M 2
Root
v2.0 High-speed Transceiver
USB FS transceiver
USB transceiver
USB transceiver
Embedded USB
SAM9X35
SAM9X35
HFSDPA
HFSDMA
HHSDPA
HHSDMA
HFSDPB
HFSDMB
HHSDPB
HHSDMB
HFSDPC
HFSDMC
527
527
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