SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 1118
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 1118 of 1325
- Download datasheet (30Mb)
46.6.2.5
46.6.2.6
1118
1118
SAM9X35
SAM9X35
DMA Interrupt Generation
DMA Address Alignment Requirements
The DMA controller operation sets the following interrupt flags in the interrupt status register
CHXISR:
When programming the DSCR.CHXADDR field of the DSCR structure the following requirement
must be met.
Table 46-5.
Table 46-6.
1 bpp
2 bpp
4 bpp
8 bpp
12 bpp RGB 444
16 bpp ARGB 4444
16 bpp RGBA 4444
16 bpp RGB 565
16 bpp TRGB 1555
18 bpp RGB 666
18 bpp RGB 666 PACKED
19 bpp TRGB 1666
19 bpp TRGB 1666
24 bpp RGB 888
24 bpp RGB 888 PACKED
25 bpp TRGB 1888
32 bpp ARGB 8888
32 bpp RGBA 8888
• DMA field indicates that the DMA transfer is completed.
• DSCR field indicates that the descriptor structure is loaded in the DMA controller.
• ADD field indicates that a descriptor has been added to the descriptor queue.
• DONE field indicates that the channel transfer has terminated and the channel is
automatically disabled.
CLUT Mode
RGB Mode
DMA address alignment when CLUT Mode is selected
DMA address alignment when RGB Mode is selected
8 bit
8 bit
8 bit
8 bit
16 bit
16 bit
16 bit
16 bit
16 bit
32 bit
8 bit
32 bit
8 bit
32 bit
8 bit
32 bit
32 bit
32 bit
DMA address alignment
DMA address alignment
11055B–ATARM–22-Sep-11
11055B–ATARM–22-Sep-11
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