CS8416-CNZ Cirrus Logic Inc, CS8416-CNZ Datasheet - Page 16

• Manufacturer Part Number: CS8416-CNZ
• Description: IC RCVR DGTL 192KHZ 28QFN COMM
• Manufacturer: Cirrus Logic Inc
• Type: Digital Audio Interface Receiverr

Specifications of CS8416-CNZ

• Applications: Digital Audio
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Audio Control Type: Digital
• Control Interface: I2C, SPI
• Control / Process Application: AV & DVD Receivers, CD-R, Digital Mixing Consoles
• Supply Voltage Range: 3.13V To 5.25V, 3.13V To 3.46V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1017 - BOARD EVAL FOR CS8416 RCVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1723

16
3. PIN DESCRIPTION - HARDWARE MODE
3.1
Pin Name
AGND
DGND
RXP0
RXP1
RXP2
RXP3
RXN
RST
FILT
VD
VA
VL
TSSOP Pin Description
Pin #
23
21
22
6
7
9
8
4
3
2
1
5
Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little
noise as possible since noise on this pin will directly affect the jitter performance of the recovered
clock
Digital Power (Input) – Digital core power supply. Nominally +3.3 V
Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be
connected to a common ground area under the chip.
Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con-
nected to a common ground area under the chip.
Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are
reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks
are stable in frequency and phase.
PLL Loop Filter (Output) - An RC network should be connected between this pin and analog
ground.
For minimum PLL jitter, return the ground end of the filter network directly to AGND. See
on page 53
Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or
S/PDIF encoded digital data. The RXP[3:0] inputs comprise the 4:2 S/PDIF Input Multiplexer. The
select line control is accessed using the RXPSEL[1:0] pins. Unused multiplexer inputs should be left
floating or tied to AGND. See
for recommended input circuits.
Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or
S/PDIF encoded digital data. Used along with RXP[3:0] to form an AES3 differential input. In single-
ended operation this should be AC coupled to ground through a capacitor. See
AES3/SPDIF/IEC60958 Receiver Components” on page 49
NV / RERR
RXSEL1
RXSEL0
TXSEL1
TXSEL0
AGND
RXP3
RXP2
RXP1
RXP0
RXN
FILT
RST
VA
for more information on the PLL and the external components.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
“External AES3/SPDIF/IEC60958 Receiver Components” on page 49
28-pin SOIC/TSSOP
Top-Down View
Package
Pin Description
28
27
26
25
24
23
22
21
20
19
18
17
16
15
for recommended input circuits.
OLRCK
OSCLK
SDOUT
OMCK
RMCK
VD
DGND
VL
TX
C
U
RCBL
96KHZ
AUDIO
“External
CS8416
“PLL Filter”
DS578F3