CS8422-CNZ Cirrus Logic Inc, CS8422-CNZ Datasheet - Page 47

• Manufacturer Part Number: CS8422-CNZ
• Description: IC SAMPLE RATE CONVERTER 32QFN
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8422-CNZ

• Package / Case: 32-QFN
• Applications: Digital Audio
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Mounting Style: SMD/SMT
• Package: 32QFN
• Operating Temperature: -55 to 125 °C
• Audio Control Type: Sample Rate Converter
• Control Interface: I2C, SPI
• Supply Voltage Range: 1.71V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Audio Ic Case Style: QFN
• No. Of Pins: 32
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1568 - BOARD EVAL FOR CS8422 RCVR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1732

DS692F1
11.SOFTWARE REGISTER BIT DEFINITIONS
The table row beneath the row that contains the register-bit name shows the register bit default value. Bits labeled
‘Reserved’ must remain at their default value.
11.1
11.2
PDN
ID4
7
0
7
1
CS8422 I.D. and Version Register (01h)
ID[4:0] - ID code for the CS8422. Permanently set to 00010
REV[2:0] = 000 (revision A)
REV[2:0] = 010 (revision B1)
Clock Control (02h)
PDN - Controls the internal clocks, allowing the CS8422 to be placed in a “powered down”, low current con-
sumption state. This bit must be written to the 0 state to allow the CS8422 to begin operation. All input clocks
should be stable in frequency and phase when PDN is set to 0.
FSWCLK – Forces the clock signal on XTI to be output on RMCK regardless of the SWCLK bit functionality
or PLL lock.
SWCLK - Outputs XTI clock signal on RMCK pin when PLL loses lock. Any OSCLK or OLRCK derived from
RMCK under normal conditions will be derived from XTI in this case.
RMCK_CTL[1:0] - RMCK Control
INT[1:0] - Interrupt output pin (INT) control
0- Normal part operation.
1- Internal clocks are stopped. Internal state machines are reset. The fully static control port is operational,
allowing registers to be read or changed. Power consumption is low.
0 – Clock signal on XTI is output on RMCK according to the SWCLK bit functionality.
1 – Forces the clock signal on XTI to be output on RMCK regardless of the SWCLK bit functionality.
0 - Disable automatic clock switching.
1 - Enable automatic clock switching on PLL unlock. Clock signal selected on XTI is automatically output
on RMCK on PLL Unlock.
00 - RMCK is an output and is derived from the frame rate of incoming AES3 data.
01 - RMCK is an output and is derived from the ISCLK input frequency divided by 64. Only valid if serial
audio input port is in slave mode (SIMS = 0 in
10 - RMCK is high-impedance.
11 - Reserved
00 - Active high; high output indicates interrupt condition has occurred.
FSWCLK
ID3
6
0
6
0
SWCLK
ID2
5
0
5
0
RMCK_CTL1 RMCK_CTL0
ID1
4
1
4
0
“Serial Audio Input Data Format (0Bh)” on page
ID0
3
0
3
0
REV2
INT1
2
0
2
0
REV1
INT0
1
0
1
0
Reserved
CS8422
REV0
53).
0
0
0
0
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