STA304A STMicroelectronics, STA304A Datasheet
STA304A
Specifications of STA304A
Available stocks
Related parts for STA304A
STA304A Summary of contents
Page 1
... OSCILLATOR VARIABLE DIGITAL GAIN UP TO 24dB (0.75dB STEP) 1.0 DESCRIPTION The STA304A Digital Audio Processor is a single chip device implementing end to end digital solution for audio application. In conjunction with STA500 power bridge it gives the full digital DSP-to-power high quality chain with no need for audio Digital-to- Analog converters between DSP and power stage ...
Page 2
... STA304A 1.0 DESCRIPTION (continued) The device supports two main configurations as far as input sources: AC'97 input or IIS/SPDIF input: selection is made via a dedicated pin (AC97_MODE pin). The AC`97 can be configured to work in two different ways: 'Full Compliant' mode and 'Proprietary' mode which enables more features. The selection of the operating mode is done via a specific bit in a Vendor Reserved register (see bit 0: AC97_FC_mode in the CRA register, address 5Ah) ...
Page 3
... AC97 Enable / Disable (1=AC97; 0=I2S/ SPDIF) I2C Serial Data I2C Serial Clock Select Address (I2C / AC97) Test Mode (Active High) Digital Supply Voltage Crystal Input (Clock input) Crystal Output Digital Ground STA304A SLEFT_B 33 VDD_4 32 GND_4 31 LEFT_A 30 LEFT_B 29 ...
Page 4
... STA304A PIN FUNCTION (continued) PIN NAME TYPE 17 VCC 18 RXP I 19 RXN I 20 VSS 21 LFE_B O 22 LFE_A O 23 SRIGHT_B O 24 SRIGHT_A O 25 GND_3 26 VDD_3 27 RIGHT_B O 28 RIGHT_A O 29 LEFT_B O 30 LEFT_A O 31 GND_4 32 VDD_4 33 SLEFT_B O 34 SLEFT_A O 35 EAPD O 36 LRCKO I/O ...
Page 5
... Note 2: Human Body Model Parameter Parameter = 3.3V ± 0.3V °C; unless otherwise specified) DD amb Parameter Test Condition Min 3. Leakage < 1µA 2000 STA304A Value Unit -0 -0.3 to VDD+0.3 V -0.3 to VDD+0.3 V °C -40 to +150 °C -20 to +85 tbd mW tbd mW Value Unit °C/W 85 Value 3 ...
Page 6
... STA304A DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Low Level Input Voltage il V High Level Input Voltage ih V Low Level Output Voltage ol V High Level Output Voltage oh Note 1: Takes into account 200mV voltage drop in both supply lines Note the source/sinc current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability. ...
Page 7
... When a write request is issued the actual data written into the RAM register is ‘xxxxxx0111xxxxxx’, where ‘x’ stands for the incoming data. • Regs. 32h and 34h: Any write request into one of these ADC sample rate register will result in the value BB80h written into the corresponding RAM register. STA304A 7/31 ...
Page 8
... STA304A 3.0 I2S INPUT INTERFACE CONFIGURATION In order to configure the I2S input interface the Configuration Register B (CRB) can be used. Using the 3 I2SI_Align_x bits one of 6 configuration mode can be selected. Following is a table describing each one of them. MODE # of SLOTS W. LENGHT Not valid Not valid ...
Page 9
... STA304A NOTES No Yes No MSb first only No No Slave only Not valid Reserved, do not use. No MSb first only. Slave only No Slave only T 1 D00AU1245 9/31 ...
Page 10
... STA304A 5.0 SAMPLE RATE CONVERTER The sample rate converter resamples the selected input data source in order to send to the DSP an audio stream with a fixed frequency of 48 KHz. The following picture show the basic architecture. Figure 4. DATA_IN Fs LRCK_IN The selection between X2 Fir interpolation or direct antialiasing Filter on input data is made automatically by the threshold selector block ...
Page 11
... The AC`97 interface can be configured either as primary or secondary device using the external configuration pin SA. This interface support 4 sampling frequencies, according to the Variable and Double Rate Audio Codec `97 LRCK SRC_Bypass SRC YRAM LEFT RIGHT SL/CENTER SR CENTER LFE PLL_Bypass MCK /1024 LRCK / CK_OUT STA304A I2C DDX YRAM LEFT DSP RIGHT SL/CENTER SR CENTER LFE I2S 11/31 ...
Page 12
... STA304A specification. The following table summarize the slot usage for each one the these frequencies: Freq. Slot 3 Slot 4 Slot 6 48 Left Right Center 44.1 Left Right 88.2 * Left Right Center 96 Left Right Center * Slots 3, 4 and 6 are always requested. Slots 10, 11 and 12 are requested only when needed. ...
Page 13
... PR5 or PWDN requests: this solution will prevent any possible noise or glitch. LR LFE DSP & Requests & OR & & STA304A LR reg. 02h bit 15 LFE reg. 36h bit 15 SR reg. 38h bit 07 SL reg. 38h bit 15 EAPD pin (ACTIVE Low) Chip powerdown Internal CK disable ...
Page 14
... STA304A 9.0 BASS MANAGEMENTAND EQ The STA304A has the ability to redirect the sound to the SBW channel and to pass each channel through a 4- stage cascaded 2nd order IIR filter. With the combination of the DDX gain/compressor (CRA register bits 2-3) a dynamic EQ can be implemented. Beside that, a special Side-Firing sound can be achieved by enabling this feature available with the ready made filter topology on the surround channels ...
Page 15
... The Side firing topology is enabled by setting Static EQ and Side Firing register (add. 70h, see section 12.12). Figure 11. Speaker System with Side-Firing positioning bi-quad0 bi-quad1 bi-quad2 bi-quad3 + bi-quad0 bi-quad1 bi-quad2 bi-quad3 STA304A Left Surround Output + and Phase Invering Right Surround Output 15/31 ...
Page 16
... STA304A 10.0 COEFFICIENT HANDLING In order to implement the Static EQ filters and the Bass management, a RAM space for user coefficients has been included in this device: starting from address 240h (YRAM) there are bit registers available for this purpose. In order to be able to read or write into these registers an indirected addressing approach must be followed by the application software ...
Page 17
... SBW02 (a2) SBW03 (a1/2) SBW04 (b1/2) SBW10 … SBW34 -scale_in LR -scale_in SUR -scale_in SBW -scale_L→SBW -scale_R→SBW -scale_LS→SBW -scale_RS→SBW -scale_C→SBW -scale_LFE→SBW STA304A default value 00000h 00000h … 00000h 00000h … 00000h 00000h … 00000h 00032h 80032h 7C7EAh ...
Page 18
... During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of 8 bits of data. 11.1.5Data input During the data input the STA304A samples the SDA signal on the rising edge of the clock SCL. For correct device operation the SDA signal has to be stable during the rising edge of the clock and the data can change only when the SCL line is low ...
Page 19
... The 8th bit (LSB) is the read or write operation RW, this bit is set read mode and 0 for write mode. After a START condition the STA304A identifies on the bus the device address and match is found, it acknowl- edges the identification on SDA bus during the 9th bit time. The following byte after the device identification byte is the internal space address ...
Page 20
... STA304A 12.0 REGISTER SUMMARY 12.1 Reset Register (add. 00h) D15 D14 D13 D12 D11 Writing any value to this register performs a register reset, which causes all registers to revert to their default values. Reading this register returns 00E4h the ID code of the part and its 3D Stereo Enhancement type (See AC'97 revision 2 ...
Page 21
... This will stop the device internal clock: only the PLL and AC`97, I still be running. DSP should start power-down sequence in order to accomplish this request. The value of this bit should be checked by the DSP in order to recognize an external power amplifier power-down request consequence the DSP should start the power-down sequence (volume fade-out) STA304A ...
Page 22
... STA304A 12.5 Extended Audio ID Register (add. 28h) D15 D14 D13 D12 D11 0 ID0 The Extended Audio read only register that identifies which extended audio features are supported (See AC'97 revision 2.1 specification, section A.2.1). The extended features supported are Variable Rate PCM Audio (VRA), Double- Rate PCM Audio (DRA), PCM Center (CDAC), PCM Surround (SDAC) and PCM LFE (LDAC) ...
Page 23
... SRC Bypass. Setting this bit to 1 the SRC block can be bypassed and the selected input I/F is directly connected to the DSP. SRC_THR_1 Threshold Frequency 0 0 INACTIVE 0 1 58.875 to 61.125kHz 1 0 78.973 to 81.000kHz 1 1 always active STA304A DDX_ZD DDX_Rst DDX_Ga DDX_Ga I2SI_DBU _Enable in_1 in_0 FF_Mode DESCRIPTION D0 ...
Page 24
... STA304A Table 2. DDX gain DDX_GAIN_0 DDX Gain Compression Since a full-scale output of the GC/Vol block is mapped to full output modulation, any signal exceeding 0 dBFS at the output of the GC/Vol block will be clipped. The purpose of the compression algorithm is to reduce the gain of the system when 0 dBFS has been exceeded such that clipping does not take place, thus performing an output limiting function ...
Page 25
... LRCK line will be an output. Otherwise (0) slave mode is selected and this line is an input. In any case the frequency is fixed at 48 kHz I2S (Output) ) MSb/LSb Selection. Use this bit to select how the sample word is transmitted by the I2S output interface: set configure as LSb first, 1 MSb first. STA304A ...
Page 26
... The STA304A provides continuous digital gain and limiting functionality. Digital gain is variable from 0dB to +23.25dB in 0.75dB steps based in the 62h register when the bit 15 is set. If the bit 15 is not set, th STA304A defaults to the original Gain/Limiting truth table based on DDX_Gain bits (12.9). The GCEN bit when set enables limiting to prevent clipping ...
Page 27
... Setting bit 0 bypass the DSP block. All channels are bypassed and output equal to input, regardless of all other algorithm register settings (Volume, Tone, Phantom, EQ). Default is 0h D10 EQ0 0 EQ off (default enabled x Side Firing + EQ D10 D10 STA304A EQ1 Bass Mng Bypass D0 EQ0 D0 27/31 ...
Page 28
... These registers are specific vendor identification for the STA304A. The Microsoft’s Plug and Play Vendor ID code is "ALJ". The REV7.. 0 field is for the Vendor Revision number. These are read only registers, any write request to one of these will be ignored. 28/31 D10 D9 D8 ...
Page 29
... inch TYP. MAX. MECHANICAL DATA 0.063 0.006 0.055 0.057 0.015 0.018 0.008 0.472 0.480 0.394 0.401 0.315 0.472 0.480 0.394 0.401 0.315 0.031 0.024 0.030 TQFP44 ( 1.4mm) 0.039 TQFP4410 STA304A OUTLINE AND 0.10mm .004 Seating Plane C K 0076922 D 29/31 ...
Page 30
... STA304A 13.0 REVISION HISTORY Date Revision Mar-2002 4 No recorded changes 26-Apr-2010 5 Major revision for revalidation process 30/31 Changes ...
Page 31
... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America Please Read Carefully: © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com STA304A 31/31 ...