STA304A STMicroelectronics, STA304A Datasheet - Page 23

• Manufacturer Part Number: STA304A
• Description: IC PROCESSOR AUD DGTL DDX 44TQFP
• Manufacturer: STMicroelectronics
• Series: DDX™r
• Type: Audio Processorr

Specifications of STA304A

• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Case: QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Applications: -
• Other names: 497-3944

12.9 Configuration Register A (CRA) : add. 5Ah
NOTE: In TEST_MODE -> PLL_Bypass = 0.
Table 1. SRC Threshold
SRC_By
D15
pass
BIT
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
DRLL_d
D14
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bg
SRC_TH
D13
R_1
RST
0
0
0
0
1
1
1
0
1
0
0
0
1
0
0
0
SRC_TH
D12
R_0
I2SI_DBUFF_Mode
DDX_ZD_Enable
AC97_FC_Mode
MCKOUT_Mode
I2S_SPDIF_Sel
DDX_PwrMode
DDX_Gain_0
DDX_Gain_1
SPDIF_Mode
SRC_Bypass
SRC_THR_0
SRC_THR_1
PLL_Bypass
PLL_Factor
DRLL_dbg
SPDIF_
DDX_Rst
SRC_THR_0
Mode
D11
NAME
0
0
1
1
DIF_Sel
I2S_SP
D10
MCKOU
T_Mode
D9
SRC_THR_1
AC’97 Full Compliant Mode (0 to enable). When in FC mode any read
of registers will return only valid bits: bits marked as ‘reserved’ by
AC’97 v2.0 specification will return 0, regardless of the RAM
contents.
Enable DoubleBuffer mode for the I2S input interface (write1 to
enable this option) . This is strongly required if this interface is
operated in slave mode at 48KHz, synchronous with the input source.
In this condition also Sample Rate Converter Bypass is suggested to
omprove performances
DDX Gain setting (LSb/MSb). These two bits, concatenated, will set
the DDX stage gain and the compression as shown in Table 1.
(These setting is active only if bit 15 reg 62h is 0)
DDX Reset (active high)
DDX Zero Detect feature. If this bit is 1 the feature is enabled.
DDX Power Mode (TRUTH Table). Using this bit it is possible to select
the truth table used by the DDX digital output stage (1 = ST standard)
PLL Factor (x2 or x8). It should be used according to the input
frequency provided to the device: 1 (x8) when 6.144 MHz are
provided, 0 (x2) when 24.576 MHz.
PLL Bypass. Setting this bit to 0 will bypass the PLL; internal master
clock will be directly connected to XTI pin.
MckOut mode: 12.288 MHz (1) or 24.576 MHz (0).
I2S - S/PDIF Selector. Select the input source: set to 0 for I2S input, 1
for S/PDIF input.
S/PDIF Mode. Set to 0 to select Analog mode, 1 to select Digital
mode.
Sample Rate threshold (LSb/MSb). These bits are used to select the
threshold frequency enabling the SRC anti-alias filter.
Table 2 shows the threshold selections.
DRLL Debug Mode. When this mode is activated (1) the DRLL digital
ratio is latched on the output channels instead of the audio data.
SRC Bypass. Setting this bit to 1 the SRC block can be bypassed and
the selected input I/F is directly connected to the DSP.
PLL_By
0
1
0
1
pass
D8
PLL_Fac
D7
tor
Threshold Frequency
58.875 to 61.125kHz
78.973 to 81.000kHz
wrMode
DDX_P
D6
always active
INACTIVE
DDX_ZD
_Enable
DESCRIPTION
D5
DDX_Rst DDX_Ga
D4
in_1
D3
DDX_Ga
in_0
D2
I2SI_DBU
FF_Mode
STA304A
D1
AC97_F
C_Mode
23/31
D0