STV8206 STMicroelectronics, STV8206 Datasheet - Page 31
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STV8206
Manufacturer Part Number
STV8206
Description
IC TV AUDIO PROC/DEMOD 80-TQFP
Manufacturer
STMicroelectronics
Type
Audio Processorr
Datasheet
1.STV8206.pdf
(97 pages)
Specifications of STV8206
Applications
Radio
Mounting Type
Surface Mount
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
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STV82x6
8
8.1
8.2
I²C Bus
I²C Address and Protocol
The STV82x6 I²C interface works in Slave mode and is fully compliant with I²C standards in Fast
mode (maximum frequency of 400 kHz). Two pairs of I²C chip addresses are used to connect two
STV82x6 chips to the same I²C serial bus. The device address pairs are defined by the polarity of
the ADR pin and are listed in the following table:
Protocol Description
The STV82x6 cannot immediately reply to an I²C read request when addressing DSP registers
(addresses 40h and greater).The I²C interface holds the I²C Serial Clock (SCL) line low before each
data byte is read to compensate for the latency of the DSP response (64 µs in worst case). The
implemented I²C Pulling Down mode is compatible with a Continuous or Stopped SCL when held
low (restart at high level, if stopped) and operates between 24 kHz and 400 kHz. If SCL Pulling
Down mode is not supported by the Master I²C interface, the Pulling Down system can be de-
activated by setting the SCLPD_OFF bit in register RESET. In this case, two successive reads of
the same DSP register are required and only the second one is valid (first read is ‘don’t care’). This
special protocol is no longer compatible with the I²C sub-address auto-incrementation function in
Read mode.
STV82x6 Reset
All STV82x6 features are controlled via the I²C bus. However, the device is designed to power up
into a fully working default mode without having to be sent I²C bus data to set it up.
The STV82x6 can be "reset" in 2 ways:
1. By Software via the I²C bus: This clears all synchronous logic, except for the I²C bus registers.
2. By Hardware via the RESET pin: In addition to clearing all synchronous logic, the RESET input
●
●
●
●
●
●
●
Write Protocol
Read Protocol
W = Write address,
R = Read address,
A = Acknowledge,
N = No acknowledge.
Sub-address is the register address pointer; this value auto-increments for both write and read.
(active low) resets all the I²C bus registers to the default values listed below.
Start
Start
HIGH (connected to VDD1)
LOW (connected to GND1)
W A
W A
ADR
Sub-address
Sub-address
Table 8: I²C Read/Write Addresses
Write address (hex) (W)
A
A
Data
Stop
A0h
80h
A
Start
....
A
R
Read address (hex) (R)
Data
A
Data
A
A1h
81h
Stop
A
....
A
Data
I²C Bus
31/97
N