STV8206 STMicroelectronics, STV8206 Datasheet - Page 41

• Manufacturer Part Number: STV8206
• Description: IC TV AUDIO PROC/DEMOD 80-TQFP
• Manufacturer: STMicroelectronics
• Type: Audio Processorr

Specifications of STV8206

• Applications: Radio
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STV82x6
9.4
Note:
Address (hex): 08h
Type: R/W
MUTE_SW
Bit Name
MUTE_HP
Bit Name
MUTE_LS
HPD_ON
Bit 7
SDIV[2:0]
FDIV[2:0
HPD_IN
SW_ON
Bits[4:3]
Bits[7:6]
0
Clocking
A low-jitter PLL Clock is integrated and can be fully reprogrammed using the registers described
below. By default, the programming is defined for a 27-MHz quartz crystal frequency, which is the
frequency recommended for reducing potential RF interference in the application. (See
2.2: System
crystal frequencies within a range from 23 to 30 MHz. Other quartz crystal frequencies can be
programmed on your demand.
A Crystal Frequency change is compatible with other default I²C programming including the built-in
Automatic Standard Recognition System.
PLL_DIV
Bit 6
Reset
Reset
0
000
000
101
00
00
Clock.) However, if necessary, the PLL Clock can be re-programmed for other quartz
0
0
0
Headphone Input Pin Status
Read only I²C bit that displays the HPD pin Status
0: Headphone is detected
1: Headphone is not detected
Headphone Detection Enable
0: Headphone Detection is disabled
1: Headphone Detection is enabled. If the HPD_IN bit is set, the Loudspeaker and Subwoofer
Subwoofer Enable
Before switching on/off the subwoofer, a mute is recommended to prevent an audible plop.
0: Subwoofer is disabled. Headphone output is selected.
1: Subwoofer is enabled. Subwoofer output is selected and Headphone output is in Mono mode
Reserved.
000: LS + SW + HP mono
001: LS + SW
010: LS + HP stereo
011: LS only
Reserved.
PLL Frequency S-Divider
PLL Frequency F-Divider
mute is activated
Bit 5
PLL Frequency Divider Register
SDIV[2:0]
Bit 4
Bit 3
100: Not used.
101: Not used.
110: HP stereo only.
111: All muted (Default)
Function
Function
Bit 2
FDIV[2:0]
Bit 1
Register List
Section
Bit 0
41/97