LPC11U14FET48 NXP Semiconductors, LPC11U14FET48 Datasheet - Page 8

The LPC11U14FET48 is a ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/

LPC11U14FET48

Manufacturer Part Number
LPC11U14FET48
Description
The LPC11U14FET48 is a ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/
Manufacturer
NXP Semiconductors
Datasheet

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Table 3.
LPC11U1X
Product data sheet
Symbol
RESET/PIO0_0
PIO0_1/CLKOUT/
CT32B0_MAT2/
USB_FTOGGLE
PIO0_2/SSEL0/
CT16B0_CAP0
PIO0_3/USB_VBUS
PIO0_4/SCL
Pin description
6.2 Pin description
Table 3
number. The default function after reset is listed first. All port pins have internal pull-up
resistors enabled after reset with the exception of the true open-drain pins PIO0_4 and
PIO0_5.
Every port pin has a corresponding IOCON register for programming the digital or analog
function, the pull-up/pull-down configuration, the repeater, and the open-drain modes.
The USART, counter/timer, and SSP functions are available on more than one port pin.
Table 4
shows all pins and their assigned digital or analog functions ordered by GPIO port
shows how peripheral functions are assigned to port pins.
2
3
8
9
10
3
4
10
14
15
All information provided in this document is subject to legal disclaimers.
C1
C2
F1
H2
G3
Rev. 2 — 11 January 2012
[2]
[3]
[3]
[3]
[4]
Reset
state
[1]
I; PU
-
I; PU
-
-
-
I; PU
-
-
I; PU
-
I; IA
-
Type
I
I/O
I/O
O
O
O
I/O
I/O
I
I/O
I
I/O
I/O
Description
RESET — External reset input with 20 ns glitch
filter. A LOW-going pulse as short as 50 ns on
this pin resets the device, causing I/O ports and
peripherals to take on their default states, and
processor execution to begin at address 0. This
pin also serves as the debug select input. LOW
level selects the JTAG boundary scan. HIGH
level selects the ARM SWD debug mode.
PIO0_0 — General purpose digital input/output
pin.
PIO0_1 — General purpose digital input/output
pin. A LOW level on this pin during reset starts
the ISP command handler.
CLKOUT — Clockout pin.
CT32B0_MAT2 — Match output 2 for 32-bit
timer 0.
USB_FTOGGLE — USB 1 ms Start-of-Frame
signal.
PIO0_2 — General purpose digital input/output
pin.
SSEL0 — Slave select for SSP0.
CT16B0_CAP0 — Capture input 0 for 16-bit
timer 0.
PIO0_3 — General purpose digital input/output
pin.
USB_VBUS — Monitors the presence of USB
bus power.
PIO0_4 — General purpose digital input/output
pin (open-drain).
SCL — I
High-current sink only if I
selected in the I/O configuration register.
32-bit ARM Cortex-M0 microcontroller
2
C-bus clock input/output (open-drain).
LPC11U1x
2
C Fast-mode Plus is
© NXP B.V. 2012. All rights reserved.
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