LPC11U24FET48 NXP Semiconductors, LPC11U24FET48 Datasheet - Page 17

• Manufacturer Part Number: LPC11U24FET48
• Description: The LPC11U24FET48 is a ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC11U2X
Product data sheet
7.6.2 Interrupt sources
7.7.1 Features
7.7 IOCON block
7.8 General-Purpose Input/Output GPIO
Each peripheral device has one interrupt line connected to the NVIC but can have several
interrupt flags. Individual interrupt flags can also represent more than one interrupt
source.
The IOCON block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Connect peripherals to the appropriate pins before activating the peripheral and before
enabling any related interrupt. . Activity of any enabled peripheral function that is not
mapped to a related pin is treated as undefined.
The GPIO registers control device pin functions that are not connected to a specific
peripheral function. Pins can be dynamically configured as inputs or outputs. Multiple
outputs can be set or cleared in one write operation.
LPC11U2x use accelerated GPIO functions:
Any GPIO pin providing a digital function can be programmed to generate an interrupt on
a level, a rising or falling edge, or both.
The GPIO block consists of three parts:
1. The GPIO ports.
2. The GPIO pin interrupt block to control eight GPIO pins selected as pin interrupts.
3. Two GPIO group interrupt blocks to control two combined interrupts from all GPIO
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Four programmable interrupt priority levels, with hardware priority level masking.
Software interrupt generation.
Programmable pull-up, pull-down, or repeater mode.
All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (V
pull-up resistor is enabled.
Programmable pseudo open-drain mode.
Programmable 10 ns glitch filter on pins PIO0_22, PIO0_23, and PIO0_11 to
PIO0_16. The glitch filter is turned off by default.
Programmable hysteresis.
Programmable input inverter.
GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
Entire port value can be written in one instruction.
pins.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 13 January 2012
32-bit ARM Cortex-M0 microcontroller
LPC11U2x
© NXP B.V. 2012. All rights reserved.
DD
= 3.3 V) if their
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