LPC2290 NXP Semiconductors, LPC2290 Datasheet - Page 20

• Manufacturer Part Number: LPC2290
• Description: The LPC2290 microcontroller is based on a 16/32-bit ARM7TDMI-S CPU with real-timeemulation and embedded trace support
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2290_3
Product data sheet
6.12.1 Features
6.13.1 Features
6.14.1 Features
6.13 SSP serial I/O controller (available in LPC2290/01 only)
6.14 General purpose timers
The LPC2290/01 contains one Serial Synchronous Port controller (SSP). The SSP
controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact
with multiple masters and slaves on the bus. However, only a single master and a single
slave can communicate on the bus during a given data transfer. The SSP supports full
duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. Often only one of these data flows carries
meaningful data.
The SSP and SPI1 share the same pins on LPC2290/01. After a reset, SPI1 is enabled
and SSP is disabled.
The TIMER0 and TIMER1 are designed to count cycles of the peripheral clock (PCLK)
and optionally generate interrupts or perform other actions at specified timer values,
based on four match registers. It also includes four capture inputs to trap the timer value
when an input signal transitions, optionally generating an interrupt. Multiple pins can be
selected to perform a single capture or match function, providing an application with ‘or’
and ‘and’, as well as ‘broadcast’ functions among them.
•
•
•
•
•
•
•
•
•
•
•
•
Compliant with SPI specification.
Synchronous, serial, full duplex, communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
Synchronous Serial Communication.
8-frame FIFOs for both transmit and receive.
Compatible with Motorola SPI, 4-wire TI SSI and National Semiconductor Microwire
buses.
Master or slave operation.
Four bits to 16 bits per SPI frame.
A 32-bit Timer/Counter with a programmable 32-bit prescaler.
Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an
interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Rev. 03 — 16 November 2006
16/32-bit ARM microcontroller with external memory interface
LPC2290
© NXP B.V. 2006. All rights reserved.
20 of 41