P87C552 NXP Semiconductors, P87C552 Datasheet - Page 63

• Manufacturer Part Number: P87C552
• Description: The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in anadvanced CMOS process and is a derivative of the 80C51microcontroller family
• Manufacturer: NXP Semiconductors

1. See Figures 57 through 60 for I
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
8. Capacitive loading on ports 0 and 2 may cause the V
9. The following condition must not be exceeded: V
10. Conditions: AV
11. The differential non-linearity (DL
12. The ADC is monotonic; there are no missing codes.
13. The integral non-linearity (IL
14. The offset error (OS
15. The gain error (G
16. The absolute voltage error (A
17. This should be considered when both analog and digital signals are simultaneously input to port 5.
18. This parameter is guaranteed by design and characterized, but is not production tested.
Philips Semiconductors
DC ELECTRICAL CHARACTERISTICS (Continued)
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
2003 Apr 01
SYMBOL
Analog Inputs (Continued)
AV
AV
R
C
t
t
t
t
DL
IL
IL
OS
OS
G
A
M
C
ADS
ADS8
ADC
ADC8
e
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I
capture/compare, high I/O, low voltage (2.7 V to 5.5 V), low power
REF
IA
e
t
e
e8
CTC
Idle Mode: I
V
V
EA = RST = STADC = XTAL1 = V
0 while an input voltage above 3.0V will be recognized as a logic 1.
current reaches its maximum value when V
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
address bits are stabilizing.
parameters from collected conversion results of ADC. AV
appropriate adjustment of gain and offset error. (See Figure 47.)
ideal transfer curve. (See Figure 47.)
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 47.)
ADC and the ideal transfer curve.
IN
REF
e
e
e8
IH
IH
= V
= V
DD
DD
Analog input voltage
Reference voltage:
Resistance between AV
Analog input capacitance
Sampling time (10 bit mode)
Sampling time (8 bit mode)
Conversion time (including sampling time, 10 bit mode)
Conversion time (including sampling time, 8 bit mode)
Differential non-linearity
Integral non-linearity
Integral non-linearity (8 bit mode)
Offset error
Offset error (8 bit mode)
Gain error
Absolute voltage error
Channel to channel matching
Crosstalk between inputs of port 5
– 0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = V
– 0.5V; XTAL2 not connected; Port 0 = EW = V
ID
AV
AV
(max) = (0.18 x FREQ. + 1.01) mA.
REF–
REF–
REF+
e
) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
10, 15
e
= 0V; AV
10, 14
) is the absolute difference between the straight line which fits the actual transfer curve, and a straight line which fits the
(10 bit mode)
e
DD
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
e
10, 13
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
DD
10, 16
= 5.0V. Measurement by continuous conversion of AV
e
) is the difference between the actual step width and the ideal step width. (See Figure 47.)
10, 11, 12
REF+
SS
test conditions, and Figure 56. Active mode: I
PARAMETER
(10 bit mode)
.
and AV
IN
17, 18
is approximately 2V.
REF–
2
DD
C, PWM,
– 0.2V < AV
OH
on ALE and PSEN to momentarily fall below the 0.9V
REF+
DD
; EA = RST = STADC = V
= 4.977V. ADC is monotonic with no missing codes.
2
DD
C specification, so an input voltage below 1.5V will be recognized as a logic
< V
63
DD
DD
; STADC = V
+ 0.2V.
DD
CONDITIONS
(max) = (0.9 x FREQ. + 1.1) mA;
0–100kHz
SS
SS
IN
TEST
= –20mV to 5.12V in steps of 0.5mV, derivating
.
.
OL
OL
can exceed these conditions provided that no
s of ALE and ports 1 and 3. The noise is due
r
r
= t
= t
f
f
= 10ns; V
= 10ns; V
AV
AV
MIN
SS
SS
10
DD
–0.2
–0.2
IL
IL
DD
= V
= V
specification when the
LIMITS
;
SS
SS
AV
AV
+ 0.5V;
+ 0.5V;
50t
24t
MAX
8t
5t
DD
DD
–60
50
15
0.4
CY
CY
1
2
1
2
1
3
1
CY
CY
+0.2
+0.2
P87C552
Product data
UNIT
LSB
LSB
LSB
LSB
LSB
LSB
LSB
k
dB
pF
%
V
V
V
s
s
s
s