P87LPC767 NXP Semiconductors, P87LPC767 Datasheet - Page 26

• Manufacturer Part Number: P87LPC767
• Description: The P87LPC767 is a 20-pin single-chip microcontroller designed forlow pin count applications demanding high-integration, low costsolutions over a wide range of performance requirements
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Keyboard Interrupt (KBI)
The Keyboard Interrupt function is intended primarily to allow a
single interrupt to be generated when any key is pressed on a
keyboard or keypad connected to specific pins of the P87LPC767,
as shown in Figure 16. This interrupt may be used to wake up the
CPU from Idle or Power Down modes. This feature is particularly
useful in handheld, battery powered systems that need to carefully
manage power consumption yet also need to be convenient to use.
The P87LPC767 allows any or all pins of port 0 to be enabled to
cause this interrupt. Port pins are enabled by the setting of bits in
2002 Mar 25
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
P2M1
BIT
P2M1.7
P2M1.6
P2M1.5
P2M1.4
P2M1.3
P2M1.2
P2M1.1, P2M1.0
Address: A4h
Not Bit Addressable
SYMBOL
ENCLK
ENT1
ENT0
P2S
P1S
P0S
—
P2S
7
FUNCTION
When P2S = 1, this bit enables Schmitt trigger inputs on Port 2.
When P1S = 1, this bit enables Schmitt trigger inputs on Port 1.
When P0S = 1, this bit enables Schmitt trigger inputs on Port 0.
When ENCLK is set and the P87LPC767 is configured to use the on-chip RC oscillator, a clock
output is enabled on the X2 pin (P2.0). Refer to the Oscillator section for details.
When set, the P.7 pin is toggled whenever Timer 1 overflows. The output frequency is therefore
one half of the Timer 1 overflow rate. Refer to the Timer/Counters section for details.
When set, the P1.2 pin is toggled whenever Timer 0 overflows. The output frequency is therefore
one half of the Timer 0 overflow rate. Refer to the Timer/Counterssection for details.
These bits, along with the matching bits in the P2M2 register, control the output configuration of
P2.1 and P2.0 respectively, as shown in Table 4.
P1S
6
Figure 15. Port 2 Mode Register 1 (P2M1)
P0S
5
ENCLK
4
23
ENT1
Due to human time scales and the mechanical delay associated with
the KBI register, as shown in Figure 17. The Keyboard Interrupt Flag
(KBF) in the AUXR1 register is set when any enabled pin is pulled
low while the KBI interrupt function is active. An interrupt will
generated if it has been enabled. Note that the KBF bit must be
cleared by software.
keyswitch closures, the KBI feature will typically allow the interrupt
service routine to poll port 0 in order to determine which key was
pressed, even if the processor has to wake up from Power Down
mode. Refer to the section on Power Reduction Modes for details.
3
ENT0
2
(P2M1.1)
1
(P2M1.0)
0
Reset Value: 00h
P87LPC767
SU01638
Product data