EM773FHN33 NXP Semiconductors, EM773FHN33 Datasheet - Page 19

• Manufacturer Part Number: EM773FHN33
• Description: The EM773 is an ARM Cortex-M0 based, low-cost 32-bit energy metering IC, designed for 8/16-bit smart metering applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
EM773
Product data sheet
CAUTION
7.16.5 APB interface
7.16.6 AHBLite
7.16.7 External interrupt inputs
7.17 Emulation and debugging
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the EM773 user manual.
The APB peripherals are located on one APB bus.
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs
serve as external interrupts (see
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four
breakpoints and two watchpoints is supported.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
3. Running an application with level CRP3 selected fully disables any access to the chip
update using a reduced set of the ISP commands.
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the UART.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 3 January 2012
Section
7.16.1).
Energy metering IC
© NXP B.V. 2012. All rights reserved.
EM773
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