PHD9NQ20T NXP Semiconductors, PHD9NQ20T Datasheet - Page 3
![Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology](/photos/41/50/415037/sot428_3d_sml.gif)
PHD9NQ20T
Manufacturer Part Number
PHD9NQ20T
Description
Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology
Manufacturer
NXP Semiconductors
Datasheet
1.PHD9NQ20T.pdf
(12 pages)
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NXP Semiconductors
PHD9NQ20T
Product data sheet
Fig 1.
Fig 3.
P
(%)
I
(A)
DM
der
100
10
10
80
60
40
20
10
0
1
3
2
function of mounting base temperature
currents as a function of drain-source voltage
Normalized total power dissipation as a
T
Safe operating area; continuous and peak drain
0
1
mb
R
DS(on)
= 25 °C; I
= V
50
DS
10
DM
/ I
D
D.C.
is single pulse
100
10
2
150
V
tp = 10 μs
100 μs
1 ms
10 ms
100 ms
All information provided in this document is subject to legal disclaimers.
DS
T
003aae674
003aae676
mb
(V)
(°C)
Rev. 03 — 16 December 2010
200
10
3
Fig 2.
Fig 4.
(%)
l
(A)
I
AS
10
D
100
80
60
40
20
10
−1
0
1
10
function of mounting base temperature
current as a function of avalanche period
Normalized continuous drain current as a
unclamped inductive load
Single-shot avalanche rating; avalanche
0
−3
N-channel TrenchMOS standard level FET
T
j
prior to avalanche = 150 °C
10
50
−2
10
100
−1
PHD9NQ20T
150
1
© NXP B.V. 2010. All rights reserved.
25 °C
T
t
AV
003aae675
003aae688
mb
(ms)
(°C)
200
10
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