PHK04P02T NXP Semiconductors, PHK04P02T Datasheet
PHK04P02T
Available stocks
Related parts for PHK04P02T
PHK04P02T Summary of contents
Page 1
... PHK04P02T P-channel vertical D-MOS logic level FET Rev. 02 — 14 December 2010 1. Product profile 1.1 General description Logic level P-channel enhancement mode Field-Effect Transistor (FET plastic package using vertical D-MOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. ...
Page 2
... ° 100 ° ° °C; pulsed All information provided in this document is subject to legal disclaimers. Rev. 02 — 14 December 2010 PHK04P02T P-channel vertical D-MOS logic level FET Graphic symbol 001aaa025 Version SOT96-1 Min Max - -16 - -16 -8 ...
Page 3
... D.C. −1 10 −2 10 − All information provided in this document is subject to legal disclaimers. Rev. 02 — 14 December 2010 PHK04P02T P-channel vertical D-MOS logic level FET 120 ≤ - Normalized continuous drain current as a function of ambient temperature 001aam075 ...
Page 4
... P −1 10 −2 10 single pulse −3 10 −6 −5 −4 −3 − All information provided in this document is subject to legal disclaimers. Rev. 02 — 14 December 2010 PHK04P02T P-channel vertical D-MOS logic level FET Min Typ - 25 001aam076 t p δ − (s) ...
Page 5
... I = -0. -0 /dt = -100 A/µ -12 All information provided in this document is subject to legal disclaimers. Rev. 02 — 14 December 2010 PHK04P02T P-channel vertical D-MOS logic level FET Min Typ Max = 25 °C - °C -0.4 -0 150 °C -0 °C ...
Page 6
... GS Fig 8. 001aam081 V GS(th) (V) −1.8 V 100 150 T (°C) j Fig 10. Gate-source threshold voltage as a function of All information provided in this document is subject to legal disclaimers. Rev. 02 — 14 December 2010 PHK04P02T P-channel vertical D-MOS logic level FET 0.7 −0.8 −1.0 −1.2 0.6 −0.9 −1.1 V 0.5 GS 0.4 −1.8 0.3 −2.5 − ...
Page 7
... Fig 12. Input, output and reverse transfer capacitances 001aam085 (nC) G Fig 14. Reverse diode current as a function of reverse All information provided in this document is subject to legal disclaimers. Rev. 02 — 14 December 2010 PHK04P02T P-channel vertical D-MOS logic level FET (pF −1 −10 − ...
Page 8
... REFERENCES JEDEC JEITA MS-012 All information provided in this document is subject to legal disclaimers. Rev. 02 — 14 December 2010 PHK04P02T P-channel vertical D-MOS logic level FET θ detail ...
Page 9
... NXP Semiconductors 8. Revision history Table 7. Revision history Document ID Release date PHK04P02T v.2 20101214 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. ...
Page 10
... In case an individual agreement is concluded only the terms and conditions of the respective All information provided in this document is subject to legal disclaimers. Rev. 02 — 14 December 2010 PHK04P02T P-channel vertical D-MOS logic level FET © NXP B.V. 2010. All rights reserved ...
Page 11
... TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 02 — 14 December 2010 PHK04P02T P-channel vertical D-MOS logic level FET Trademarks © NXP B.V. 2010. All rights reserved ...
Page 12
... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 14 December 2010 Document identifier: PHK04P02T ...