PHKD6N02LT NXP Semiconductors, PHKD6N02LT Datasheet

Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology

PHKD6N02LT

Manufacturer Part Number
PHKD6N02LT
Description
Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology
Manufacturer
NXP Semiconductors
Datasheet

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1. Product profile
1.1 General description
1.2 Features and benefits
1.3 Applications
1.4 Quick reference data
Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
Table 1.
Symbol
V
I
P
Static characteristics
R
Dynamic characteristics
Q
D
DS
tot
DSon
GD
Low conduction losses due to low
on-state resistance
Battery chargers
DC-to-DC convertors
PHKD6N02LT
Dual N-channel TrenchMOS logic level FET
Rev. 04 — 27 April 2010
Quick reference data
Parameter
drain-source voltage
drain current
total power
dissipation
drain-source on-state
resistance
gate-drain charge
Conditions
T
T
conducting; see
see
T
V
V
T
j
sp
sp
j
GS
GS
≥ 25 °C; T
= 25 °C; see
= 25 °C; Single device
= 25 °C; see
Figure 3
= 2.5 V; I
= 5 V; I
D
j
= 6 A; V
≤ 150 °C
D
= 3 A; T
Figure 11
Figure
Figure 2
Suitable for logic level gate drive
sources
Notebook computers
Portable equipment
DS
j
1;
= 25 °C
= 16 V;
Min
-
-
-
-
-
Product data sheet
Typ
-
-
-
25
6
Max Unit
20
10.9 A
4.17 W
35
-
V
mΩ
nC

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PHKD6N02LT Summary of contents

Page 1

... PHKD6N02LT Dual N-channel TrenchMOS logic level FET Rev. 04 — 27 April 2010 1. Product profile 1.1 General description Dual logic level N-channel enhancement mode Field-Effect Transistor (FET plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. ...

Page 2

... Figure °C; see Figure °C sp ≤ 10 µs; pulsed ° All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 PHKD6N02LT Graphic symbol mbk725 Version SOT96-1 Min Typ Max ...

Page 3

... T (°C) sp Fig All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 PHKD6N02LT Dual N-channel TrenchMOS logic level FET 120 P der (%) 100 Normalized total power dissipation as a function of solder point temperature = 10 μ ...

Page 4

... Transient thermal impedance from junction to ambient as a function of pulse duration PHKD6N02LT Product data sheet Conditions see Figure 4 minimum footprint; mounted on printed-circuit board single pulse −2 10 All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 PHKD6N02LT Dual N-channel TrenchMOS logic level FET Min Typ - - - −1 ...

Page 5

... G(ext °C; see /dt = -100 A/µ ° All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 PHKD6N02LT Min Typ Max 0.5 - 1 500 - - 100 - - 100 - 25 ...

Page 6

... V (V) GS Fig 8. junction temperature All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 PHKD6N02LT Dual N-channel TrenchMOS logic level FET = 150 ° ° Transfer characteristics: drain current as a max min ...

Page 7

... D Fig 10. Normalized drain-source on-state resistance 003aaa307 (nC) G Fig 12. Input, output and reverse transfer capacitances All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 PHKD6N02LT Dual N-channel TrenchMOS logic level FET 2 a 1.5 1 0.5 0 − factor as a function of junction temperature ...

Page 8

... Product data sheet ( 150 ° ° 0.2 0.4 0.6 0.8 All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 PHKD6N02LT Dual N-channel TrenchMOS logic level FET 003aaa306 1 V (V) SD © NXP B.V. 2010. All rights reserved ...

Page 9

... REFERENCES JEDEC JEITA MS-012 All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 PHKD6N02LT Dual N-channel TrenchMOS logic level FET θ detail ...

Page 10

... Dual N-channel TrenchMOS logic level FET Data sheet status Change notice Product data sheet - Product data sheet - Product data - Product data - All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 PHKD6N02LT Supersedes PHKD6N02LT_3 PHKD6N02LT-02 PHKD6N02LT-01 - © NXP B.V. 2010. All rights reserved ...

Page 11

... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 PHKD6N02LT Dual N-channel TrenchMOS logic level FET © NXP B.V. 2010. All rights reserved ...

Page 12

... TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 PHKD6N02LT Dual N-channel TrenchMOS logic level FET Trademarks © NXP B.V. 2010. All rights reserved ...

Page 13

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 27 April 2010 Document identifier: PHKD6N02LT ...

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