STM32F101C8 STMicroelectronics, STM32F101C8 Datasheet - Page 16

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STM32F101C8

Manufacturer Part Number
STM32F101C8
Description
Mainstream Access line, ARM Cortex-M3 MCU with 64 Kbytes Flash, 36 MHz CPU
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F101C8

Peripherals Supported
timers, ADC, SPIs, I2Cs and USARTs
Conversion Range
0 to 3.6 V
Systick Timer
24-bit downcounter

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Description
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10
16/87
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 36 MHz. See
Boot modes
At startup, boot pins are used to select one of three boot options:
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
Power supply schemes
For more details on how to connect power pins, refer to
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
generated when V
DD
/V
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
V
Provided externally through V
V
and PLL (minimum voltage to be applied to V
V
V
registers (through power switch) when V
DD
SSA
DDA
BAT
DDA
= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
, V
= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
power supply and compares it to the V
and V
DDA
SSA
= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
DD
must be connected to V
/V
DD
DDA
is below a specified threshold, V
drops below the V
Doc ID 13586 Rev 14
Figure 2
DD
pins.
for details on the clock tree.
DD
DD
PVD
and V
is not present.
PVD
threshold and/or when V
DDA
SS
threshold. An interrupt can be
is 2.4 V when the ADC is used).
Figure 11: Power supply
, respectively.
POR/PDR
STM32F101x8, STM32F101xB
, without the need for an
DD
/V
DDA
scheme.
is higher

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