STM32F051C4 STMicroelectronics, STM32F051C4 Datasheet - Page 10
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STM32F051C4
Manufacturer Part Number
STM32F051C4
Description
Entry-level ARM Cortex-M0 MCU with 16 Kbytes Flash, 48 MHz CPU, motor control and CEC functions
Manufacturer
STMicroelectronics
Datasheet
1.STM32F051C6.pdf
(40 pages)
Specifications of STM32F051C4
Voltage Range
2.0 V to 3.6 V
Conversion Range
0 to 3.6V
Systick Timer
24-bit downcounter
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Quantity
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Manufacturer:
STMicroelectronics
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Functional overview
3
3.1
3.2
3.3
10/22
Functional overview
ARM
The ARM Cortex™-M0 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M0 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F051xx family has an embedded ARM core and is therefore compatible with all
ARM tools and software.
Figure 1
Memories
The device has the following features:
●
●
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 96-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
Up to 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0
wait states and featuring embedded parity checking with exception generation for fail-
critical applications.
The non-volatile memory is divided into two arrays:
–
–
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
–
–
–
®
shows the general block diagram of the device family.
16 to 64 Kbytes of embedded Flash memory for programs and data
Option bytes
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and boot
in RAM selection disabled
Cortex
TM
-M0 core with embedded Flash and SRAM
Doc ID 018746 Rev 2
STM32F051x