STM32F415ZG STMicroelectronics, STM32F415ZG Datasheet - Page 128
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STM32F415ZG
Manufacturer Part Number
STM32F415ZG
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, HW crypto
Manufacturer
STMicroelectronics
Datasheet
1.STM32F415ZG.pdf
(168 pages)
Specifications of STM32F415ZG
Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Cryptographic Acceleration
hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1), and HMAC
Rtc
subsecond accuracy, hardware calendar
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F415ZGT6
Manufacturer:
VISHAY
Quantity:
5 000
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Electrical characteristics
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Figure 52. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 71.
1. C
2. Based on characterization, not tested in production.
t
t
su(Data_NOE)
t
t
h(Data_NOE)
t
t
t
t
su(Data_NE)
v(NADV_NE)
h(NE_NOE)
v(NOE_NE)
t
h(BL_NOE)
h(Data_NE)
L
t
Symbol
t
h(A_NOE)
t
v(BL_NE)
t
w(NADV)
v(A_NE)
= 30 pF.
t
w(NOE)
w(NE)
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
FSMC_NE low time
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
Address hold time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NOE high
Data to FSMC_NEx high setup time
Data to FSMC_NOEx high setup time
Data hold time after FSMC_NOE high
Data hold time after FSMC_NEx high
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
Doc ID 022063 Rev 2
Parameter
STM32F415xx, STM32F417xx
2T
2T
T
T
HCLK
HCLK
HCLK
HCLK
Min
0.5
4
0
-
-
0
0
0
-
-
–0.5 2 T
+4
+4
–2
2T
T
HCLK
Max
HCLK
HCLK
4.5
1.5
3
2
-
-
-
-
-
-
-
+ 2
+1
(1)(2)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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