STM32F415ZG STMicroelectronics, STM32F415ZG Datasheet - Page 137
STM32F415ZG
Manufacturer Part Number
STM32F415ZG
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, HW crypto
Manufacturer
STMicroelectronics
Datasheet
1.STM32F415ZG.pdf
(168 pages)
Specifications of STM32F415ZG
Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Cryptographic Acceleration
hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1), and HMAC
Rtc
subsecond accuracy, hardware calendar
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F415ZGT6
Manufacturer:
VISHAY
Quantity:
5 000
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STM32F415xx, STM32F417xx
PC Card/CompactFlash controller waveforms and timings
Figure 60
provide the corresponding timings. The results shown in this table are obtained with the
following FSMC configuration:
●
●
●
●
●
●
●
●
●
●
●
●
●
●
In all timing tables, the
Figure 60. PC Card/CompactFlash controller waveforms for common memory read
1. FSMC_NCE4_2 remains high (inactive during 8-bit access.
FSMC_NCE4_2
COM.FSMC_SetupTime = 0x04;
COM.FSMC_WaitSetupTime = 0x07;
COM.FSMC_HoldSetupTime = 0x04;
COM.FSMC_HiZSetupTime = 0x00;
ATT.FSMC_SetupTime = 0x04;
ATT.FSMC_WaitSetupTime = 0x07;
ATT.FSMC_HoldSetupTime = 0x04;
ATT.FSMC_HiZSetupTime = 0x00;
IO.FSMC_SetupTime = 0x04;
IO.FSMC_WaitSetupTime = 0x07;
IO.FSMC_HoldSetupTime = 0x04;
IO.FSMC_HiZSetupTime = 0x00;
TCLRSetupTime = 0;
TARSetupTime = 0.
FSMC_NCE4_1
FSMC_NIOWR
FSMC_NIORD
FSMC_D[15:0]
FSMC_A[10:0]
FSMC_NREG
FSMC_NWE
FSMC_NOE
through
access
t d(NCE4_1-NOE)
(1)
Figure 65
T
HCLK
represent synchronous waveforms, and
is the HCLK clock period.
Doc ID 022063 Rev 2
t d(NREG-NCEx)
t d(NIORD-NCEx)
t v(NCEx-A)
t w(NOE)
t su(D-NOE)
t h(NCEx-NREG)
t h(NCEx-NIORD)
t h(NCEx-NIOWR)
t h(NCEx-AI)
Electrical characteristics
t h(NOE-D)
Table 79
and
ai14895b
Table 80
137/168
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