STM32F101RE STMicroelectronics, STM32F101RE Datasheet - Page 110
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STM32F101RE
Manufacturer Part Number
STM32F101RE
Description
Mainstream Access line, ARM Cortex-M3 MCU with 512 Kbytes Flash, 36 MHz CPU
Manufacturer
STMicroelectronics
Datasheet
1.STM32F101VD.pdf
(112 pages)
Specifications of STM32F101RE
Core
ARM 32-bit Cortex™-M3 CPU
Conversion Range
0 to 3.6 V
Peripherals Supported
timers, ADC, DAC, SPIs, I2Cs and USARTs
Systick Timer
a 24-bit downcounter
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F101RET6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Revision history
110/112
Table 66.
21-Jul-2009
Date
Document revision history (continued)
Revision
6
Figure 1: STM32F101xC, STM32F101xD and STM32F101xE access
line block diagram
Note 5
STM32F101xx pin
V
voltage.
f
characteristics.
Table 23: HSE 4-16 MHz oscillator characteristics
modified below
Figure 44: Recommended NRST pin protection
replaced by C in
Table 24: LSE oscillator characteristics (fLSE = 32.768
modified and moved below the tables.
Table 25: HSI oscillator characteristics
from
Jitter added to
In
timings: t
In
timings: t
In
t
In
t
In
t
In
cycles: t
Table 54: SPI characteristics
C
R
Table 59: DAC characteristics
buffered DAC
HSE_ext
h(AD_NADV)
h(A_NWE)
h(CLKH-NWAITV)
RERINT
ADC
AIN
Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read
Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write
Table 33: Asynchronous multiplexed NOR/PSRAM read
Table 34: Asynchronous multiplexed NOR/PSRAM write
Table 35: Synchronous multiplexed NOR/PSRAM read
Table 40: Switching characteristics for NAND Flash read and write
Doc ID 14610 Rev 8
Table 27: Low-power mode wakeup
max values modified in
and R
updated and
h(NOE-D)
min modified in
and T
h(BL_NOE)
h(A_NWE)
modified.
and t
AIN
added.
Coeff
Table 28: PLL
Figure 19: Typical application with an 8 MHz
modified.
parameters modified in
Table 23: HSE 4-16 MHz oscillator characteristics
h(A_NOE)
modified.
STM32F101xC, STM32F101xD, STM32F101xE
and t
modified.
definitions.
and t
added to
Note 4
h(Data_NWE)
h(A_NOE)
Table 21: High-speed external user clock
modified.
added in
Table 56: RAIN max for fADC = 14
Table 13: Embedded internal reference
modified.
characteristics.
modified.
Changes
modified.
modified.
Table 5: High-density
modified. Conditions removed
Table 55: ADC
Figure 53: 12-bit buffered /non-
timings.
modified. C
modified.
characteristics.
kHz), notes
timings:
timings:
timings:
L1
Note 1
crystal.
and C
MHz.
and
L2