STM32W108C8 STMicroelectronics, STM32W108C8 Datasheet - Page 165

• Manufacturer Part Number: STM32W108C8
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with 64-Kybte Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108C8

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch and breakpoint; data watchpoint and trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108C8
Table 108. Typical ADC input configurations (continued)
Input range
ADC inputs can be routed through input buffers to expand the input voltage range. The input
buffers have a fixed 0.25 gain and the converted data is scaled by that factor.
With the input buffers disabled the single-ended input range is 0 to VREF and the differential
input range is -VREF to +VREF. With the input buffers enabled the single-ended range is 0
to VDD_PADS and the differential range is -VDD_PADS to +VDD_PADS.
The input buffers are enabled for the ADC P and N inputs by setting the ADC_HVSELP and
ADC_HVSELN bits respectively, in the ADC_CFG register. The ADC accuracy is reduced
when the input buffer is selected.
Sample time
ADC sample time is programmed by selecting the sampling clock and the clocks per
sample.
●
●
Table 109
results.
Table 109. ADC sample times
ADC5
GND
VREF
VDD_PADSA/2
ADC_PERIOD
ADC P input
The sampling clock may be either 1 MHz or 6 MHz. If the ADC_1MHZCLK bit in the
ADC_CFG register is clear, the 6 MHz clock is used; if it is set, the 1 MHz clock is
selected. The 6 MHz sample clock offers faster conversion times but the ADC
resolution is lower than that achieved with the 1 MHz clock.
The number of clocks per sample is determined by the ADC_PERIOD bits in the
ADC_CFG register. ADC_PERIOD values select from 32 to 4096 sampling clocks in
powers of two. Longer sample times produce more significant bits. Regardless of the
sample time, converted samples are always 16-bits in size with the significant bits left-
aligned within the value.
0
1
2
3
4
5
shows the options for ADC sample times and the significant bits in the conversion
Sample
clocks
1024
128
256
512
32
64
VREF/2
ADC4
VREF/2
VREF/2
ADC N input
1 MHz clock 6 MHz clock 1 MHz clock 6 MHz clock
1024
128
256
512
Sample time (µs)
32
64
Doc ID 018587 Rev 2
5.33
10.7
21.3
42.7
85.3
ADC_MUXP
170
10
11
5
8
Sample frequency (kHz)
0.977
31.3
15.6
7.81
3.91
1.95
ADC_MUXN
Analog-to-digital converter
4
9
9
9
93.8
46.9
23.4
11.7
5.86
188
Calibration
Differential
Calibration
Calibration
Purpose
Significant
bits
10
5
6
7
8
9
164/215