ST72325S4 STMicroelectronics, ST72325S4 Datasheet - Page 16

• Manufacturer Part Number: ST72325S4
• Description: 8-BIT MCU WITH 16 TO 60K FLASH/ROM, ADC, CSS, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72325S4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST72325xx
Notes for
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V
are not implemented). See See “I/O PORTS” on page 50. and
ISTICS
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscil-
lator; see
more details.
4. On the chip, each I/O port may have up to 8 pads:
– In all devices except 48-pin ST72325C, pads that are not bonded to external pins are forced by hardware
– In 48-pin ST72325C devices, unbonded pads PA0, PA1, PB6, PB7, PD6, PD7, PE3, PE5, PE6, PE7,
5.
6.
pins to ground.
16/197
28 31 PB0/PWM3
29 32 PB3/PWM0
30
31
32
Pin n°
in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to
avoid added current consumption.
PF3 and PF5) are in input floating configuration after reset. To avoid added current consumption, the
application must force these ports in input pull-up state by writing to the OR and DDR registers after re-
set. This initialization is not necessary in 48-pin ST72325S devices.
Pull-up always activated on PE2 see limitation
It is mandatory to connect all available V
1
2
3
for more details.
PB4 (HS)/ARTCLK
PD0/AIN0
PD1/AIN1
Table 2
Section 1 DESCRIPTION
Pin Name
and
Table
I/O C
I/O C
I/O C
I/O C
I/O C
3:
Level
T
T
T
T
T
HS
and
Section 12.5 CLOCK AND TIMING CHARACTERISTICS
X
X
X
X
X
DD
X
X
Input
ei2
ei3
and V
ei2
Port
Section
REF
X
X
Output
pins to the supply voltage and all V
X
X
X
X
X
15.1.8.
Section 12.8 I/O PORT PIN CHARACTER-
X
X
X
X
X
function
Port B0
Port B3
Port B4
Port D0
Port D1
reset)
(after
Main
PWM Output 3
Caution: Negative current injec-
tion not allowed on this pin
PWM Output 0
PWM-ART External Clock
ADC Analog Input 0
ADC Analog Input 1
Alternate function
SS
and V
SSA
for
DD