ST72262G1 STMicroelectronics, ST72262G1 Datasheet - Page 20

• Manufacturer Part Number: ST72262G1
• Description: 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72262G1

• 4 K Or 8 Kbytes Program Memory: ROM or single voltage extended Flash (XFlash) with read-out protection, write protection, In-Circuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt,Wait and Slow
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes

ST72260Gx, ST72262Gx, ST72264Gx
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in
For more details, refer to dedicated parametric
section.
Main Features
■
■
■
■
Figure 10. Clock, Reset and Supply Block Diagram
20/172
RESET
OSC2
OSC1
V
V
– 4 Crystal/Ceramic resonator oscillators
– 1 Internal RC oscillator
– Main supply Low Voltage Detector (LVD)
– Auxiliary Voltage Detector (AVD) with inter-
Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)
Reset Sequence Manager (RSM)
Multi-Oscillator Clock Management (MO)
System Integrity Management (SI)
SS
DD
rupt capability for monitoring the main supply
OSCILLATOR
RESET SEQUENCE
MULTI-
(MO)
MANAGER
(RSM)
Figure
f
OSC
10.
(option)
PLL
SYSTEM INTEGRITY MANAGEMENT
SICSR
0
AVD AVD LVD
IE
AVD Interrupt Request
AUXILIARY VOLTAGE
F
LOW VOLTAGE
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the 2 to
4 MHz range, the PLL can be used to multiply the
frequency by two to obtain an f
The PLL is enabled by option byte. If the PLL is
disabled, then f
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
“PLL Characteristics” on page 139.
Figure 9. PLL Block Diagram
RF
DETECTOR
DETECTOR
f
OSC
(AVD)
(LVD)
0
0
0
PLL x 2
WDG
f
OSC2 =
OSC2
/ 2
RF
CLOCK (MCC/RTC)
f
OSC
WITH REALTIME
MISCR1 Register
TIMER (WDG)
CONTROLLER
MAIN CLOCK
SLOW MODE
WATCHDOG
PLL OPTION BIT
SELECTION
/2.
OSC2
0
1
of 4 to 8 MHz.
f
f
OSC2
to CPU
and
Peripherals
CPU