ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 104

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

On-chip peripherals
10.4.6
Note:
Caution:
10.4.7
10.4.8
104/193
Low power modes
Table 53.
Using the SPI to wake up the MCU from Halt mode
In slave configuration, the SPI is able to wake up the ST7 device from Halt mode through a
SPIF interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from Halt mode state to normal
state. If the SPI exits from Slave mode, it returns to normal state immediately.
The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. Therefore,
if Slave selection is configured as external (see
make sure the master drives a low level on the SS pin when the slave enters Halt mode.
Interrupts
Table 54.
1. The SPI interrupt events are connected to the same interrupt vector (see
SPI registers
SPI control register (SPICR)
SPI end of transfer event
Master mode fault event
Overrun error
SPICR
Mode
Wait
Halt
generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC
register is reset (RIM instruction).
SPIE
R/W
Interrupt event
7
No effect on SPI.
SPI interrupt events cause the device to exit from Wait mode.
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an
interrupt with Exit from Halt mode capability. The data received is subsequently read from
the SPIDR register when the software is running (interrupt vector fetching). If several data
are received before the wakeup event, then an overrun error is generated. This error can
be detected after the fetch of the interrupt routine that woke up the device.
Effect of low power modes on SPI
SPI interrupt control/wakeup capability
SPE
R/W
6
SPR2
R/W
Event flag
5
MODF
SPIF
OVR
MSTR
R/W
4
Enable control bit
Description
SPIE
Slave select management on page
CPOL
R/W
3
(1)
CPHA
Exit from Wait
R/W
Section 7:
2
Reset value: 0000 xxxx (0xh)
Yes
Interrupts). They
1
SPR[1:0]
Exit from Halt
R/W
ST72324Bxx
Yes
No
98),
0