ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 35

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

ST72324Bxx
Figure 14. Reset block diagram
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
External power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V
the minimum level specified for the selected f
A proper reset signal for a slow rising V
RC network connected to the RESET pin.
Internal LVD reset
Two different reset sequences caused by the internal LVD circuitry can be distinguished:
●
●
The device RESET pin acts as an output that is pulled low when V
V
The LVD filters spikes on V
Internal Watchdog reset
The reset sequence generated by a internal Watchdog counter overflow is shown in
Figure
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least t
DD
< V
Power-On reset
Voltage Drop reset
15.
IT-
RESET
(falling edge) as shown in
V
DD
DD
w(RSTL)out
R
larger than t
ON
Figure
.
Filter
DD
g(VDD)
supply can generally be provided by an external
15.
OSC
to avoid parasitic resets.
frequency.
Supply, reset and clock management
generator
Pulse
DD
< V
Watchdog reset
LVD reset
IT+
Internal
reset
(rising edge) or
DD
is over
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