ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 122

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

On-chip peripherals
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Table 62.
SCI Control Register 1 (SCICR1)
Table 63.
SCICR1
Bit
Bit Name
7
6
5
4
3
2
0
R/W
R8
7
WAKE
Name
SCID
PCE
PE
R8
T8
M
SCISR register description (continued)
SCICR1 register description
Parity error
Receive data bit 8
Transmit data bit 8
Disabled for low power consumption
Word length
Wakeup method
Parity control enable
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared
by a software sequence (a read to the status register followed by an access to the
SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
1: Parity error
R/W
This bit is used to store the 9th bit of the received word when M = 1.
This bit is used to store the 9th bit of the transmitted word when M = 1.
When this bit is set the SCI prescalers and outputs are stopped and the end of the
current byte transfer in order to reduce power consumption.This bit is set and
cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 data bits, 1 Stop bit
1: 1 Start bit, 9 data bits, 1 Stop bit
Note: The M bit must not be modified during a data transfer (both transmission and
reception).
This bit determines the SCI wakeup method, it is set or cleared by software.
0: Idle line
1: Address mark
This bit selects the hardware parity control (generation and detection). When the
parity control is enabled, the computed parity is inserted at the MSB position (9th bit
if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set
and cleared by software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
0: Parity control disabled
1: Parity control enabled
T8
6
SCID
R/W
5
R/W
M
4
Function
Function
WAKE
R/W
3
PCE
R/W
2
Reset value: x000 0000 (x0h)
R/W
PS
1
ST72324Bxx
R/W
PIE
0