ST72321AR9-Auto STMicroelectronics, ST72321AR9-Auto Datasheet - Page 67

• Manufacturer Part Number: ST72321AR9-Auto
• Description: 8-bit MCU for automotive with 60 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
8.4.2
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status
register (MCCSR) is cleared (see
beeper (MCC/RTC) on page 82
The MCU can exit Halt mode on reception of either a specific interrupt (see
20.: Interrupt mapping on page
RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU
cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching the reset vector which woke it up (see
Figure
When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the ‘WDGHALT’
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog RESET (see
configuration on page 223
Figure 27. Halt timing overview
28).
[MCCSR.OIE = 0]
INSTRUCTION
RUN
HALT
for more details).
HALT
Doc ID 13829 Rev 1
56) or a RESET. When exiting Halt mode by means of a
for more details on the MCCSR register).
Section 11: Main clock controller with real-time clock and
256 OR 4096 CPU
CYCLE DELAY
INTERRUPT
RESET
OR
VECTOR
FETCH
Section 21.1.1: Flash
RUN
Power saving modes
Section Table
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