ST72334N4 STMicroelectronics, ST72334N4 Datasheet - Page 131

• Manufacturer Part Number: ST72334N4
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72334N4

• Clock Sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
• 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Two 16-bit Timers With: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes

16.9 CONTROL PIN CHARACTERISTICS
16.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V
Figure 90. Typical Application with RESET pin
Notes:
1. Unless otherwise specified, typical data are based on T
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The I
(I/O ports and control pins) must not exceed I
5. The R
scribed in
6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on
RESET pin with a duration below t
7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environments.
8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
t
w(RSTL)out
t
t
Symbol
h(RSTL)in
g(RSTL)in
V
R
V
V
V
EXTERNAL
CIRCUIT
hys
OL
ON
IH
IL
RESET
USER
IO
ON
current sunk must always respect the absolute maximum rating specified in
Figure
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Output low level voltage
(see
Weak pull-up equivalent resistor
Generated reset pulse duration
External reset pulse hold time
Filtered glitch duration
pull-up equivalent resistor is based on a resistive transistor (corresponding I
8)
Figure
91). This data is based on characterization results, not tested in production.
V
DD
0.1 F
0.1 F
92,
Parameter
V
Figure
DD
4.7k
h(RSTL)in
2)
93)
7)
2)
4)
6)
can be ignored.
5)
VSS
3)
.
DD
V
V
External pin or
internal reset sources
, f
DD
IN
RESET
OSC
=5V
8)
V
A
Conditions
SS
=25°C and V
, and T
R
ON
I
I
V
V
IO
IO
DD
DD
V
=+5mA
=+2mA
DD
=5V
=3.4V
A
ST72334J/N, ST72314J/N, ST72124J
unless otherwise specified.
DD
=5V.
0.7xV
Min
20
80
20
DD
Section 16.2.2
ON
Typ
0.68
0.28
400
100
40
30
6
current characteristics de-
1)
INTERNAL
RESET CONTROL
WATCHDOG RESET
LVD RESET
0.3xV
and the sum of I
Max
0.95
0.45
120
100
60
DD
ST72XXX
1/f
131/153
Unit
SFOSC
mV
k
ns
V
V
s
s
IO