ST10R272L STMicroelectronics, ST10R272L Datasheet - Page 18

• Manufacturer Part Number: ST10R272L
• Description: 16-BIT Romless MCU WITH MAC UNIT
• Manufacturer: STMicroelectronics

Specifications of ST10R272L

• Cpu Frequency: 0 to 50 MHz
• Power: 3.3 Volt +/-0.3V

ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)
The Parallel Data Move shifts a table of operands in parallel with a computation on those
operands. Its specific use is for signal processing algorithms like filter computation. The
following figure gives an example of Parallel Data Move with CoMACM instruction.
16 x 16 signed/unsigned parallel multiplier
The multiplier executes 16 x 16-bit parallel signed/unsigned fractional and integer multiplies.
The multiplier has two 16-bit input ports, and a 32-bit product output port. The input ports can
accept data from the MA-bus and from the MB-bus. The output is sign-extended and then
feeds a scaler that shifts the multiplier output according to the shift mode bit MP specified in
the co-processor Control Word (MCW). The product can be shifted one bit left to compensate
for the extra sign bit gained in multiplying two 16-bit signed (2’s complement) fractional
numbers if bit MP is set.
40-bit signed arithmetic unit
The arithmetic unit over 32 bits wide to allow intermediate overflow in a series of multiply/
accumulate operations. The extension flag E, contained in the most significant byte of MSW,
is set when the Accumulator has overflowed beyond the 32-bit boundary, that is, when there
are significant (non-sign) bits in the top eight (signed arithmetic) bits of the Accumulator.
The 40-bit arithmetic unit has two 40-bit input ports A and B. The A-input port accepts data
from 4 possible sources: 00,0000,0000h, 00,0000,8000h (round), the sign-extended product,
or the sign-extended data conveyed by the 32-bit bus resulting from the concatenation of MA-
and MB-buses. Product and Concatenation can be shifted left by one according to MP for the
multiplier or to the instruction for the concatenation. The B-input port is fed either by the 40-bit
shifted/not shifted and inverted/not inverted accumulator or by 00,0000,0000h. A-input and B-
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1
n+2
n
n-2
n-4
Before Execution
16-bit
X
Figure 6 Example of parallel data move
IDX0
CoMACM [IDX0+], [R2+]
n+2
n
n-2
n-4
After Execution
X
X
Parallel Data Move
IDX0