ST72321AR6 STMicroelectronics, ST72321AR6 Datasheet - Page 107

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ST72321AR6

Manufacturer Part Number
ST72321AR6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72321AR6

Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt,Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.9 Clock Deviation Causes
The causes which contribute to the total deviation
are:
All the deviations of the system should be added
and compared to the SCI clock tolerance:
D
Figure 63. Bit Sampling in Reception Mode
RDI LINE
TRA
– D
– D
– D
– D
Sample
clock
oscillator error of the transmitter or the trans-
mitter is transmitting at a different baud rate).
tion of the receiver.
receiver: This deviation can occur during the
reception of one complete SCI message as-
suming that the deviation has been compen-
sated at the beginning of the message.
(generally due to the transceivers)
+ D
TRA
QUANT
REC
TCL
: Deviation due to the transmission line
QUANT
: Deviation due to transmitter error (Local
: Deviation of the local oscillator of the
: Error due to the baud rate quantiza-
+ D
1
REC
2
+ D
TCL
3
< 3.75%
7/16
4
5
6
One bit time
7
sampled values
10.6.4.10 Noise Error Causes
See also description of Noise error in
0.1.4.3
Start bit
The noise flag (NF) is set during start bit reception
if one of the following conditions occurs:
1. A valid falling edge is not detected. A falling
2. During sampling of the 16 samples, if one of the
Therefore, a valid Start Bit must satisfy both the
above conditions to prevent the Noise Flag getting
set.
Data Bits
The noise flag (NF) is set during normal data bit re-
ception if the following condition occurs:
– During the sampling of 16 samples, if all three
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise
Flag getting set.
8
samples numbered 8, 9 and10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
edge is considered to be valid if the 3 consecu-
tive samples before the falling edge occurs are
detected as '1' and, after the falling edge
occurs, during the sampling of the 16 samples,
if one of the samples numbered 3, 5 or 7 is
detected as a “1”.
samples numbered 8, 9 or 10 is detected as a
“1”.
9
ST72321Rx ST72321ARx ST72321Jx
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Section
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