ST72321AR6 STMicroelectronics, ST72321AR6 Datasheet - Page 116

• Manufacturer Part Number: ST72321AR6
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH,10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72321AR6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST72321Rx ST72321ARx ST72321Jx
I
Acknowledge may be enabled and disabled by
software.
The I
dress can be selected by software.
The speed of the I
between Standard (up to 100KHz) and Fast I
(up to 400KHz).
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
Figure 65. I
116/193
2
C BUS INTERFACE (Cont’d)
SCL or SCLI
SDA or SDAI
2
C interface address and/or general call ad-
2
C Interface Block Diagram
2
C interface may be selected
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
DATA CONTROL
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL REGISTER (CR)
2
C
The SCL frequency (F
grammable clock divider which depends on the
I
When the I
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
When the I
ports revert to being standard I/O port pins.
2
OWN ADDRESS REGISTER 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
C bus mode.
DATA SHIFT REGISTER
DATA REGISTER (DR)
CONTROL LOGIC
COMPARATOR
INTERRUPT
2
2
C cell is disabled, the SDA and SCL
C cell is enabled, the SDA and SCL
scl
) is controlled by a pro-