DS2408 Maxim, DS2408 Datasheet - Page 27

• Manufacturer Part Number: DS2408
• Description: The DS2408 is an 8-channel, programmable I/O 1-Wire® chip
• Manufacturer: Maxim

3) The input buffer was designed with hysteresis. If a negative glitch crosses V
4) There is a time window specified by the rising edge hold-off time t
Figure 15. NOISE SUPPRESSION SCHEME
CRC GENERATION
The DS2408 has two different types of cyclic redundancy checks (CRCs). One CRC is an 8-bit type and
is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from
the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2408 to determine if
the ROM data has been received error free. The equivalent polynomial function of this CRC is X
X
into the ROM.
The other CRC is a 16-bit type, generated according to the standardized CRC16-polynomial function X
+ X
page using the Read PIO Registers command, for fast verification of the data transfer when writing to or
reading from the scratchpad, and when reading from the PIO using the Channel-access Read command.
In contrast to the 8-bit CRC, the 16-bit CRC is always communicated in the inverted form. A CRC-
generator inside the DS2408 chip (Figure 16) calculates a new 16-bit CRC as shown in the command
flow chart of Figure 8. The bus master compares the CRC value read from the device to the one it
calculates from the data and decides whether to continue with an operation or to reread the portion of the
data with the CRC error.
With the Read PIO Registers flow chart, the 16-bit CRC value is the result of shifting the command byte
into the cleared CRC generator, followed by the 2 address bytes and the data bytes beginning at the target
address and ending with the last byte of the register page, address 008Fh.
With the initial pass through the Channel-access Read command flow, the CRC is generated by first
clearing the CRC generator and then shifting in the command code followed by 32 bytes of PIO pin data.
Subsequent passes through the command flow will generate a 16-bit CRC that is the result of clearing the
CRC generator and then shifting in 32 bytes read from the PIO pins. For more information on generating
CRC values see Application Note 27.
4
+ 1. This 8-bit CRC is received in the true (noninverted) form. It is computed at the factory and lasered
V
V
speed.
ignored, even if they extend below the V
voltage droops or glitches that appear late after crossing the V
window cannot be filtered out and will be taken as the beginning of a new time slot (Figure 15, Case
C, t
15
HY
TH
V
+ X
V
GL
PUP
0V
TH
- V
≥ t
2
+ 1. This CRC is used for error detection when reading data through the end of the register
HY
REH
, it will not be recognized (Figure 15, Case A). The hysteresis is effective at any 1-Wire
).
Case A
t
GL
Case B
TH
t
REH
27 of 39
- V
HY
threshold (Figure 15, Case B, t
TH
threshold and extend beyond the t
REH
t
REH
t
Case C
GL
during which glitches will be
TH
but doesn’t go below
GL
< t
REH
8
). Deep
DS2408
+ X
REH
5
16
+