TDA18254HN/C1,518 NXP Semiconductors, TDA18254HN/C1,518 Datasheet - Page 20

• Manufacturer Part Number: TDA18254HN/C1,518
• Description: IC CABLE TUNER DGTL 48HVQFN
• Manufacturer: NXP Semiconductors
• Type: Tunerr

Specifications of TDA18254HN/C1,518

• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935289589518

NXP Semiconductors
7. Register descriptions
SC16C852V
Product data sheet
6.14.3.2 Auto address detection
If Special Character Detect is enabled (EFR[5] is set and the XOFF2 register contains the
address byte), the receiver will try to detect an address byte that matches the
programmed character in the XOFF2 register. If the received byte is a data byte or an
address byte that does not match the programmed character in the XOFF2 register, the
receiver will discard these data. Upon receiving an address byte that matches the Xoff2
character, the receiver will be automatically enabled if not already enabled, and the
address character is pushed into the RX FIFO along with the parity bit (in place of the
parity error bit). The receiver also generates a line status interrupt (IER[2] must be set to
logic 1 at this time). The receiver will then receive the subsequent data from the ‘master’
station until being disabled by the controller after having received a message from the
‘master’ station.
If another address byte is received and this address byte does not match Xoff2 character,
the receiver will be automatically disabled and the address byte is ignored. If the address
byte matches Xoff2 character, the receiver will put this byte in the RX FIFO along with the
parity bit in the parity error bit (LSR bit 2).
Table 9
assigned bit functions are more fully defined in
details the assigned bit functions for the SC16C852V internal registers. The
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
Section 7.1
through
SC16C852V
Section
© NXP B.V. 2011. All rights reserved.
7.23.
20 of 55