TDA18254HN/C1,518 NXP Semiconductors, TDA18254HN/C1,518 Datasheet - Page 6

• Manufacturer Part Number: TDA18254HN/C1,518
• Description: IC CABLE TUNER DGTL 48HVQFN
• Manufacturer: NXP Semiconductors
• Type: Tunerr

Specifications of TDA18254HN/C1,518

• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935289589518

NXP Semiconductors
Table 2.
SC16C852V
Product data sheet
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
CDA
CDB
CS
CTSA
CTSB
DSRA
DSRB
DTRA
DTRB
Pin description
Pin
TFBGA36
A3
B3
A2
B2
A1
B1
C3
C1
B4
F3
E2
A6
F6
A5
E4
C5
B6
5.2 Pin description
HVQFN48
44
45
46
47
48
1
2
3
40
16
10
38
23
39
20
34
35
Fig 5.
TFBGA36 ball mapping (transparent top view)
Type Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
O
O
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
A
B
C
D
E
F
Address and Data bus (bidirectional). These pins are the 8-bit multiplexed
data bus and address bus for transferring information to or from the controlling
CPU. AD0 is the least significant bit and is address A0 during the address
cycle, and AD7 is the most significant bit and is address A7 during the address
cycle.
Carrier Detect (active LOW). These inputs are associated with individual
UART channels A through B. A logic 0 on this pin indicates that a carrier has
been detected by the modem for that channel.
Chip Select (active LOW). This pin enables the data transfers between the
host and the SC16C852V for the addressed channel. Individual channel
selection is done with address A6. When A6 is 0 channel A is selected, and
when A6 is 1 channel B is selected.
Clear to Send (active LOW). These inputs are associated with individual
UART channels, A through B. A logic 0 on the CTS pin indicates the modem or
data set is ready to accept transmit data from the SC16C852V. Status can be
tested by reading MSR[4].
Data Set Ready (active LOW). These inputs are associated with individual
UART channels, A through B. A logic 0 on this pin indicates the modem or data
set is powered-on and is ready for data exchange with the UART. Status can be
tested by reading MSR[5].
Data Terminal Ready (active LOW). These outputs are associated with
individual UART channels, A through B. A logic 0 on this pin indicates that the
SC16C852V is powered-on and ready. This pin can be controlled via the
Modem Control Register. Writing a logic 1 to MCR[0] will set the DTR output to
logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to
MCR[0], or after a reset.
LOWPWR
RXA
AD4
AD5
AD7
TXB
Rev. 5 — 21 January 2011
1
XTAL2
RXB
AD2
AD3
TXA
CS
2
XTAL1
CDB
AD0
AD1
AD6
IOW
3
DSRB
CDA
V
V
RIA
IOR
4
DD
SS
RESET
DSRA
DTRA
RTSB
INTA
RIB
5
SC16C852V
CTSA
DTRB
CTSB
002aac352
RTSA
INTB
LLA
6
© NXP B.V. 2011. All rights reserved.
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