KTS 6027-2 Infineon Technologies, KTS 6027-2 Datasheet - Page 18

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KTS 6027-2

Manufacturer Part Number
KTS 6027-2
Description
IC TUNER MOPLL ANALOG 28-TSSOP
Manufacturer
Infineon Technologies
Type
Tunerr
Series
OMNITUNE™r
Datasheet

Specifications of KTS 6027-2

Package / Case
28-TSSOP
Applications
NTSC, PAL
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 20 C
Mounting Style
SMD/SMT
Packages
PG-TSSOP-28
Vs (min)
4.5 V
Vs (max)
5.5 V
Icc (max)
79.0 mA
Esd Protection (max)
2.0 kV
Mounting
SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
SP000013185
KTS6027-2, KTS6029-2
Functional Description
while SCL remains HIGH. All further information transfer takes place during
SCL = LOW, and the data is forwarded to the control logic on the positive clock
edge.
The table ”Bit Allocation” (
) should be
see Table 5-4 Bit Allocation Read / Write on page 31
referred to the following description. All telegrams are transmitted byte-by-byte,
followed by a ninth clock pulse, during which the control logic returns the SDA
line to LOW (acknowledge condition). The first byte is comprised of seven
address bits. These are used by the processor to select the PLL from several
peripheral components (chip select). The LSB bit (R/W) determines whether
data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte.
If the address byte indicates a READ operation, the PLL generates an acknowl-
edge and then shifts out the status byte onto the SDA line. If the processor gen-
erates an acknowledge, a further status byte is output; otherwise the data line
is released to allow the processor to generate a stop condition. The status word
consists the lock flag and the power-on flag.
Four different chip addresses can be set by appropriate DC level at pin AS (
see
).
Table 5-6 Address selection on page 32
While applying the supply voltage, a power-on reset circuit prevents the PLL
from setting the SDA line to LOW, which would block the bus. The power-on
reset flag POR is set at power-on and when V
falls below 3.2 V. It will be reset
CC
at the end of a READ operation.
Wireless Components
3 - 11
Specification, July 2001

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