STV2050A STMicroelectronics, STV2050A Datasheet - Page 64

• Manufacturer Part Number: STV2050A
• Description: IC DGTL CONVERGENCE PROC 80-PQFP
• Manufacturer: STMicroelectronics
• Type: Videor

Specifications of STV2050A

• Applications: HDTV
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STV2050A - IC STATUS REGISTERS
– Wait until the HSYNC and VSYNC signals are available on pins 27 and 28 respectively. (At
– Use the I²C master to read the EEPROMadd[2:0] data bits in the EEPROM having the hard-
Note: This is particularly suitable when it is necessary to recover the last configuration used before switch-
– Use the I²C master to download all convergence data and registers (from the selected EEP-
– Wait for up to 2 fields after all the data has been downloaded and enable the outputs.
16 IC STATUS REGISTERS
Some registers of the STV2050A can be read via the I²C slave bus in order to indicate the up-
dated status of the IC. The update is enabled using the RUE bit in the EF register.
The update timing of registers D0 to D3 is determined by the RU1 bit in the EF register.
The update timing of the E4 register is determined by the RU2 bit in the EF register.
The S01 bit in the E3 or E4 or E5 or E9 registers:
– Power-on reset status
The S02 bit in the E3 register:
– Security output (POUT) status
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least 2 VSYNC pulses are required). If one signal is missing, the STV2050A remains in
Stand-by mode.
ware address 010 (bin). The EEPROMadd[2:0] bits represent the address of the EEPROM
which will be used to setup the STV2050A during the boot sequence,
ROM, as explained before),
ing off for example.
RUE
RU1
RU2
S01
S02
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
No update
Update enabled
No update
Update after vertical reset
No update
Update after vertical reset
Reset successfully achieved
Reset ongoing
“0” (pull down to ground)
High impedance