IDT74ALVCH16245PAG IDT, Integrated Device Technology Inc, IDT74ALVCH16245PAG Datasheet - Page 5

• Manufacturer Part Number: IDT74ALVCH16245PAG
• Description: IC TRANSCVR TRI-ST 16BIT 48TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 74ALVCHr

Specifications of IDT74ALVCH16245PAG

• Logic Type: Transceiver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 8
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Logic Family: ALVC
• Operating Supply Voltage (typ): 2.5/3.3V
• Propagation Delay Time: 5.7ns
• Number Of Elements: 2
• Number Of Channels: 16
• Input Logic Level: LVTTL
• Output Logic Level: LVTTL
• Output Type: 3-State
• Package Type: TSSOP
• Polarity: Non-Inverting
• Logical Function: Bus Transceiver
• Operating Supply Voltage (min): 2.3V
• Quiescent Current (typ): 100nA
• Technology: CMOS
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH16245PAG; 800-1554; 800-1554-5; 800-1554

TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
SWITCH POSITION
NOTES:
1.
2.
Pulse
Generator
DEFINITIONS:
C
R
IDT74ALVCH16245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
L
T
Symbol
V
= Termination resistance: should be equal to Z
= Load capacitance: includes jig and probe capacitance.
V
V
For t
For t
LOAD
V
V
C
HZ
LZ
OUTPUT 2
IH
OUTPUT 1
T
L
(1, 2)
SK
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
(o) OUTPUT1 and OUTPUT2 are any two outputs.
All Other Tests
INPUT
Disable High
Disable Low
Enable High
Enable Low
Open Drain
V
CC
Test
(1)
V
IN
= 3.3V±0.3V V
300
300
2.7
1.5
50
6
Test Circuit for All Outputs
t
SK
R
(x)
Output Skew - t
T
D.U.T.
= t
V
t
PLH1
CC
PLH2
CC
t
PLH2
(1)
300
300
2.7
1.5
50
6
= 2.7V
t
V
-
SK
t
OUT
PLH1
(x)
OUT
SK
F
F
(
≤ 2ns; t
t
or
X
V
≤ 2.5ns; t
C
of the Pulse Generator.
PHL1
)
CC
L
t
t
PHL2
PHL2
(2)
2 x Vcc
Switch
Vcc / 2
= 2.5V±0.2V
V
GND
Open
R
Vcc
150
150
t
LOAD
30
500Ω
SK
500Ω
R
≤ 2ns.
ALVC Link
-
≤ 2.5ns.
t
(x)
PHL1
ALVC Link
V
V
0V
V
V
V
V
V
V
Open
IH
OH
OL
OH
OL
V
GND
T
T
T
Unit
mV
mV
LOAD
pF
V
V
V
5
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
ASYNCHRONOUS
SYNCHRONOUS
INPUT TRANSITION
INPUT TRANSITION
OPPOSITE PHASE
NORMALLY
NORMALLY
CONTROL
HIGH-LOW-HIGH
CONTROL
CONTROL
LOW-HIGH-LOW
OUTPUT
OUTPUT
SAME PHASE
TIMING
INPUT
INPUT
INPUT
HIGH
DATA
LOW
Set-up, Hold, and Release Times
OUTPUT
PULSE
Enable and Disable Times
PULSE
CLOSED
SWITCH
SWITCH
ENABLE
Propagation Delay
OPEN
t
Pulse Width
t
PZL
PZH
INDUSTRIAL TEMPERATURE RANGE
t
t
PLH
PLH
V
t
V
0V
SU
t
SU
T
V
LOAD/2
T
t
W
t
t
PHZ
REM
t
H
t
t
PHL
PHL
t
ABLE
t
H
PLZ
DIS-
ALVC Link
ALVC Link
ALVC Link
V
V
ALVC Link
V
V
0V
V
V
V
V
V
0V
T
T
0V
0V
V
V
V
V
V
V
V
IH
T
LOAD/2
LZ
OL
OH
HZ
IH
T
OH
T
OL
IH
T
V
V
0V
V
V
0V
V
V
0V
V
V
0V
IH
IH
IH
IH
T
T
T
T