TLE 8264-2E Infineon Technologies, TLE 8264-2E Datasheet - Page 11
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TLE 8264-2E
Manufacturer Part Number
TLE 8264-2E
Description
Manufacturer
Infineon Technologies
Datasheet
1.TLE_8264-2E.pdf
(94 pages)
Specifications of TLE 8264-2E
Packages
PG-DSO-36
Transceiver
High Speed CAN ISO 11898 - 5 / 3 x LIN2.0 / J2602
Voltage Regulator Output
2 x 200 mA + 400 mA
Watchdog
Standard and Window Watchdog
Quiescent Current (max.)
28 ?A (typ) Sleep Mode (5V on)
Standby Current
58 ?A (typ) Stop Mode (5V on)
4.2
The System Basis Chip (SBC) offers ten operating modes: Power On Reset, Init, Normal, Restart, Software Flash,
Sleep, Stop, Fail-Safe, Software Development, and Factory Flash Mode. The modes are controlled with one test
pin and via three mode select bits MS2..0, within the SPI. Additionally, the SBC allows five configurations,
accessed via two external pins and one SPI bit.
4.2.1
Table 1
Table 1
Configuration
config 0
config 1
config 2
config 3
config 4
In SBC SW Development Mode, Config 1 to 4 are accessible.
4.2.2
At
reaches the reset threshold
In the event that
behavior of the SBC blocks, please refer to the chapter specific to each block.
4.2.3
At entering the SBC Init Mode, the SBC starts to read the Test pin. The SBC starts-up in SBC Init Mode, and, after
powering-up, waits for the microcontroller to finish its startup and initialization sequences.
Watchdog is configurable but not active. CAN and LIN modules are inactive and Limp Home output is inactive.
From this transition mode, the SBC can be switched via SPI command to the desired operating mode, SBC Normal
or Software Flash Mode. If the SBC does not receive any SPI command, or receive wrong SPI command (i.e. not
send the device to SBC Normal or SBC SW Flash Mode) within a 256 ms time frame after the reset relaxation, it
will enter into SBC Restart Mode and activate the Limp Home output.
Note: In Init Mode it is recommended to send one SPI command that sets the device to Normal Mode, triggers the
Data Sheet
V
S
watchdog the first time and sets the required watchdog settings.
>
V
provides descriptions and conditions for entry to the different configurations of the SBC.
UVON
State Machine Description
Configuration Description
SBC Configuration
SBC Power ON Reset (POR)
SBC Init Mode
, the SBC starts to operate, by reading the test pin and then by turning ON
V
Description
Software Development Mode
After missing the WD trigger for the first time, the state of
remain unchanged, LH pin is active, SBC in Restart Mode
After missing the WD trigger for the first time,
LH pin is active, SBC in Fail-Safe Mode
After missing the WD trigger for the second time, the state of
V
Mode
After missing the WD trigger for the second time,
OFF, LH pin is active, SBC in Fail-Safe Mode
s
cc1µC
decreases below
remain unchanged, LH pin is active, SBC in Restart
V
RT1
, the reset output remains activated for t
V
UVOFF
, the device is completely disabled. For more details on the disable
11
V
cc1µC
V
turns OFF,
cc1µC
RD1
V
turns
cc1µC
and the SBC enters then the Init Mode.
Test pin
0V
Open /
V
S
V
Rev. 1.0, 2009-03-31
cc2/3
INT Pin
n.a
External
pull-up
No ext.
pull-up
External
pull-up
No ext.
pull-up
V
cc1µC
are OFF and the
TLE8264-2E
State Machine
. When
WD to
LH bit
n.a
0
0
1
1
V
cc1µC